mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 03:10:12 +00:00
drm/nouveau: rename nv40_mpeg to nv31_mpeg
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
9698b9a680
commit
323dcac552
4 changed files with 29 additions and 29 deletions
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@ -21,7 +21,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nv40_grctx.o nv50_grctx.o nvc0_grctx.o \
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nv84_crypt.o \
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nva3_copy.o nvc0_copy.o \
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nv40_mpeg.o nv50_mpeg.o \
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nv31_mpeg.o nv50_mpeg.o \
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nv04_instmem.o nv50_instmem.o nvc0_instmem.o \
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nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \
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nv50_cursor.o nv50_display.o \
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@ -1195,8 +1195,8 @@ extern int nva3_copy_create(struct drm_device *dev);
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/* nvc0_copy.c */
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extern int nvc0_copy_create(struct drm_device *dev, int engine);
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/* nv40_mpeg.c */
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extern int nv40_mpeg_create(struct drm_device *dev);
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/* nv31_mpeg.c */
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extern int nv31_mpeg_create(struct drm_device *dev);
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/* nv50_mpeg.c */
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extern int nv50_mpeg_create(struct drm_device *dev);
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@ -634,7 +634,7 @@ nouveau_card_init(struct drm_device *dev)
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}
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if (dev_priv->card_type == NV_40)
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nv40_mpeg_create(dev);
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nv31_mpeg_create(dev);
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else
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if (dev_priv->card_type == NV_50 &&
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(dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
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@ -26,7 +26,7 @@
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#include "nouveau_drv.h"
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#include "nouveau_ramht.h"
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struct nv40_mpeg_engine {
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struct nv31_mpeg_engine {
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struct nouveau_exec_engine base;
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};
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@ -81,7 +81,7 @@ nv40_mpeg_context_del(struct nouveau_channel *chan, int engine)
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}
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static int
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nv40_mpeg_object_new(struct nouveau_channel *chan, int engine,
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nv31_mpeg_object_new(struct nouveau_channel *chan, int engine,
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u32 handle, u16 class)
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{
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struct drm_device *dev = chan->dev;
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@ -103,10 +103,10 @@ nv40_mpeg_object_new(struct nouveau_channel *chan, int engine,
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}
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static int
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nv40_mpeg_init(struct drm_device *dev, int engine)
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nv31_mpeg_init(struct drm_device *dev, int engine)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv40_mpeg_engine *pmpeg = nv_engine(dev, engine);
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struct nv31_mpeg_engine *pmpeg = nv_engine(dev, engine);
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int i;
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/* VPE init */
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@ -137,7 +137,7 @@ nv40_mpeg_init(struct drm_device *dev, int engine)
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}
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static int
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nv40_mpeg_fini(struct drm_device *dev, int engine, bool suspend)
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nv31_mpeg_fini(struct drm_device *dev, int engine, bool suspend)
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{
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/*XXX: context save? */
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nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
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@ -146,7 +146,7 @@ nv40_mpeg_fini(struct drm_device *dev, int engine, bool suspend)
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}
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static int
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nv40_mpeg_mthd_dma(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
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nv31_mpeg_mthd_dma(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
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{
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struct drm_device *dev = chan->dev;
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u32 inst = data << 4;
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@ -184,7 +184,7 @@ nv40_mpeg_mthd_dma(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
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}
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static int
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nv40_mpeg_isr_chid(struct drm_device *dev, u32 inst)
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nv31_mpeg_isr_chid(struct drm_device *dev, u32 inst)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ctx;
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@ -205,7 +205,7 @@ nv40_mpeg_isr_chid(struct drm_device *dev, u32 inst)
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}
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static void
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nv40_vpe_set_tile_region(struct drm_device *dev, int i)
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nv31_vpe_set_tile_region(struct drm_device *dev, int i)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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@ -216,10 +216,10 @@ nv40_vpe_set_tile_region(struct drm_device *dev, int i)
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}
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static void
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nv40_mpeg_isr(struct drm_device *dev)
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nv31_mpeg_isr(struct drm_device *dev)
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{
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u32 inst = (nv_rd32(dev, 0x00b318) & 0x000fffff) << 4;
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u32 chid = nv40_mpeg_isr_chid(dev, inst);
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u32 chid = nv31_mpeg_isr_chid(dev, inst);
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u32 stat = nv_rd32(dev, 0x00b100);
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u32 type = nv_rd32(dev, 0x00b230);
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u32 mthd = nv_rd32(dev, 0x00b234);
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@ -249,10 +249,10 @@ nv40_mpeg_isr(struct drm_device *dev)
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}
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static void
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nv40_vpe_isr(struct drm_device *dev)
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nv31_vpe_isr(struct drm_device *dev)
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{
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if (nv_rd32(dev, 0x00b100))
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nv40_mpeg_isr(dev);
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nv31_mpeg_isr(dev);
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if (nv_rd32(dev, 0x00b800)) {
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u32 stat = nv_rd32(dev, 0x00b800);
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@ -262,9 +262,9 @@ nv40_vpe_isr(struct drm_device *dev)
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}
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static void
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nv40_mpeg_destroy(struct drm_device *dev, int engine)
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nv31_mpeg_destroy(struct drm_device *dev, int engine)
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{
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struct nv40_mpeg_engine *pmpeg = nv_engine(dev, engine);
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struct nv31_mpeg_engine *pmpeg = nv_engine(dev, engine);
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nouveau_irq_unregister(dev, 0);
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@ -273,34 +273,34 @@ nv40_mpeg_destroy(struct drm_device *dev, int engine)
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}
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int
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nv40_mpeg_create(struct drm_device *dev)
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nv31_mpeg_create(struct drm_device *dev)
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{
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struct nv40_mpeg_engine *pmpeg;
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struct nv31_mpeg_engine *pmpeg;
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pmpeg = kzalloc(sizeof(*pmpeg), GFP_KERNEL);
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if (!pmpeg)
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return -ENOMEM;
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pmpeg->base.destroy = nv40_mpeg_destroy;
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pmpeg->base.init = nv40_mpeg_init;
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pmpeg->base.fini = nv40_mpeg_fini;
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pmpeg->base.destroy = nv31_mpeg_destroy;
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pmpeg->base.init = nv31_mpeg_init;
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pmpeg->base.fini = nv31_mpeg_fini;
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pmpeg->base.context_new = nv40_mpeg_context_new;
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pmpeg->base.context_del = nv40_mpeg_context_del;
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pmpeg->base.object_new = nv40_mpeg_object_new;
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pmpeg->base.object_new = nv31_mpeg_object_new;
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/* ISR vector, PMC_ENABLE bit, and TILE regs are shared between
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* all VPE engines, for this driver's purposes the PMPEG engine
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* will be treated as the "master" and handle the global VPE
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* bits too
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*/
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pmpeg->base.set_tile_region = nv40_vpe_set_tile_region;
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nouveau_irq_register(dev, 0, nv40_vpe_isr);
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pmpeg->base.set_tile_region = nv31_vpe_set_tile_region;
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nouveau_irq_register(dev, 0, nv31_vpe_isr);
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NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
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NVOBJ_CLASS(dev, 0x3174, MPEG);
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NVOBJ_MTHD (dev, 0x3174, 0x0190, nv40_mpeg_mthd_dma);
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NVOBJ_MTHD (dev, 0x3174, 0x01a0, nv40_mpeg_mthd_dma);
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NVOBJ_MTHD (dev, 0x3174, 0x01b0, nv40_mpeg_mthd_dma);
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NVOBJ_MTHD (dev, 0x3174, 0x0190, nv31_mpeg_mthd_dma);
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NVOBJ_MTHD (dev, 0x3174, 0x01a0, nv31_mpeg_mthd_dma);
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NVOBJ_MTHD (dev, 0x3174, 0x01b0, nv31_mpeg_mthd_dma);
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#if 0
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NVOBJ_ENGINE_ADD(dev, ME, &pme->base);
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