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arm64: dts: qcom: sm8250: Add cpuidle states
This change adds various idle states and add devices to power domains. Cc: devicetree@vger.kernel.org Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1641749107-31979-3-git-send-email-quic_mkshah@quicinc.com
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1 changed files with 105 additions and 0 deletions
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@ -98,6 +98,8 @@ CPU0: cpu@0 {
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capacity-dmips-mhz = <448>;
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capacity-dmips-mhz = <448>;
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dynamic-power-coefficient = <205>;
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dynamic-power-coefficient = <205>;
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next-level-cache = <&L2_0>;
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next-level-cache = <&L2_0>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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@ -120,6 +122,8 @@ CPU1: cpu@100 {
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capacity-dmips-mhz = <448>;
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capacity-dmips-mhz = <448>;
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dynamic-power-coefficient = <205>;
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dynamic-power-coefficient = <205>;
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next-level-cache = <&L2_100>;
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next-level-cache = <&L2_100>;
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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@ -139,6 +143,8 @@ CPU2: cpu@200 {
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capacity-dmips-mhz = <448>;
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capacity-dmips-mhz = <448>;
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dynamic-power-coefficient = <205>;
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dynamic-power-coefficient = <205>;
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next-level-cache = <&L2_200>;
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next-level-cache = <&L2_200>;
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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@ -158,6 +164,8 @@ CPU3: cpu@300 {
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capacity-dmips-mhz = <448>;
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capacity-dmips-mhz = <448>;
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dynamic-power-coefficient = <205>;
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dynamic-power-coefficient = <205>;
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next-level-cache = <&L2_300>;
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next-level-cache = <&L2_300>;
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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@ -177,6 +185,8 @@ CPU4: cpu@400 {
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capacity-dmips-mhz = <1024>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <379>;
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dynamic-power-coefficient = <379>;
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next-level-cache = <&L2_400>;
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next-level-cache = <&L2_400>;
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power-domains = <&CPU_PD4>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu4_opp_table>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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@ -196,6 +206,8 @@ CPU5: cpu@500 {
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capacity-dmips-mhz = <1024>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <379>;
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dynamic-power-coefficient = <379>;
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next-level-cache = <&L2_500>;
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next-level-cache = <&L2_500>;
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power-domains = <&CPU_PD5>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu4_opp_table>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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@ -216,6 +228,8 @@ CPU6: cpu@600 {
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capacity-dmips-mhz = <1024>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <379>;
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dynamic-power-coefficient = <379>;
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next-level-cache = <&L2_600>;
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next-level-cache = <&L2_600>;
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power-domains = <&CPU_PD6>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu4_opp_table>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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@ -235,6 +249,8 @@ CPU7: cpu@700 {
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capacity-dmips-mhz = <1024>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <444>;
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dynamic-power-coefficient = <444>;
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next-level-cache = <&L2_700>;
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next-level-cache = <&L2_700>;
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power-domains = <&CPU_PD7>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 2>;
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qcom,freq-domain = <&cpufreq_hw 2>;
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operating-points-v2 = <&cpu7_opp_table>;
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operating-points-v2 = <&cpu7_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
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@ -281,6 +297,42 @@ core7 {
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};
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};
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};
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};
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};
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};
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idle-states {
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entry-method = "psci";
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LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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idle-state-name = "silver-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <360>;
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exit-latency-us = <531>;
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min-residency-us = <3934>;
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local-timer-stop;
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};
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BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
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compatible = "arm,idle-state";
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idle-state-name = "gold-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <702>;
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exit-latency-us = <1061>;
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min-residency-us = <4488>;
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local-timer-stop;
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};
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};
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domain-idle-states {
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "domain-idle-state";
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idle-state-name = "cluster-llcc-off";
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arm,psci-suspend-param = <0x4100c244>;
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entry-latency-us = <3264>;
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exit-latency-us = <6562>;
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min-residency-us = <9987>;
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local-timer-stop;
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};
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};
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};
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};
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cpu0_opp_table: cpu0_opp_table {
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cpu0_opp_table: cpu0_opp_table {
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@ -594,6 +646,59 @@ pmu {
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psci {
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psci {
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compatible = "arm,psci-1.0";
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compatible = "arm,psci-1.0";
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method = "smc";
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method = "smc";
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CPU_PD0: cpu0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD1: cpu1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD2: cpu2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD3: cpu3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD4: cpu4 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CPU_PD5: cpu5 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CPU_PD6: cpu6 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CPU_PD7: cpu7 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CLUSTER_PD: cpu-cluster0 {
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#power-domain-cells = <0>;
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domain-idle-states = <&CLUSTER_SLEEP_0>;
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};
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};
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};
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reserved-memory {
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reserved-memory {
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