mirrors
/
linux-stable
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
1
0
Fork 0
Code Issues Releases Wiki Activity

EDAC/amd64: Split read_mc_regs() into dct/umc functions 

Call them from their respective hw_info_get() paths.

ECC symbol size is not needed on UMC systems, so determine_ecc_sym_sz()
is left out of the UMC path. Do not save TOP_MEM* values on modern
controllers because they're not needed there (read: they were used only
for debugging, if anything).

  [ Yazen: rebased/reworked patch and reworded commit message. ]

Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com>
Co-developed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
Co-developed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230127170419.1824692-16-yazen.ghannam@amd.com
This commit is contained in:
Muralidhara M K 2023-01-27 17:04:12 +00:00 committed by Borislav Petkov (AMD)
parent 78ec161a91
commit 32ecdf8688
1 changed files with 4 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/edac/amd64_edac.c
View File

@ -3089,7 +3089,7 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
/*
* Retrieve the hardware registers of the memory controller.
*/
static void __read_mc_regs_df(struct amd64_pvt *pvt)
static void umc_read_mc_regs(struct amd64_pvt *pvt)
{
u8 nid = pvt->mc_node_id;
struct amd64_umc *umc;
@ -3113,7 +3113,7 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt)
* Retrieve the hardware registers of the memory controller (this includes the
* 'Address Map' and 'Misc' device regs)
*/
static void read_mc_regs(struct amd64_pvt *pvt)
static void dct_read_mc_regs(struct amd64_pvt *pvt)
{
unsigned int range;
u64 msr_val;
@ -3134,12 +3134,6 @@ static void read_mc_regs(struct amd64_pvt *pvt)
edac_dbg(0, " TOP_MEM2 disabled\n");
}
if (pvt->umc) {
__read_mc_regs_df(pvt);
goto skip;
}
amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
read_dram_ctl_register(pvt);
@ -3180,9 +3174,6 @@ static void read_mc_regs(struct amd64_pvt *pvt)
amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1);
}
skip:
determine_ecc_sym_sz(pvt);
}
@ -3658,7 +3649,7 @@ static int dct_hw_info_get(struct amd64_pvt *pvt)
dct_prep_chip_selects(pvt);
dct_read_base_mask(pvt);
read_mc_regs(pvt);
dct_read_mc_regs(pvt);
dct_determine_memory_type(pvt);
return 0;
@ -3672,7 +3663,7 @@ static int umc_hw_info_get(struct amd64_pvt *pvt)
umc_prep_chip_selects(pvt);
umc_read_base_mask(pvt);
read_mc_regs(pvt);
umc_read_mc_regs(pvt);
umc_determine_memory_type(pvt);
return 0;