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net: phy: dp83867: fix speed 10 in sgmii mode
For supporting 10Mps speed in SGMII mode DP83867_10M_SGMII_RATE_ADAPT bit of DP83867_10M_SGMII_CFG register has to be cleared by software. That does not affect speeds 100 and 1000 so can be done on init. Signed-off-by: Max Uvarov <muvarov@gmail.com> Cc: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 changed files with 17 additions and 0 deletions
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@ -30,6 +30,8 @@
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#define DP83867_STRAP_STS1 0x006E
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#define DP83867_RGMIIDCTL 0x0086
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#define DP83867_IO_MUX_CFG 0x0170
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#define DP83867_10M_SGMII_CFG 0x016F
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#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
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#define DP83867_SW_RESET BIT(15)
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#define DP83867_SW_RESTART BIT(14)
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@ -277,6 +279,21 @@ static int dp83867_config_init(struct phy_device *phydev)
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DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
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}
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if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
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/* For support SPEED_10 in SGMII mode
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* DP83867_10M_SGMII_RATE_ADAPT bit
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* has to be cleared by software. That
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* does not affect SPEED_100 and
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* SPEED_1000.
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*/
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ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
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DP83867_10M_SGMII_CFG,
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DP83867_10M_SGMII_RATE_ADAPT_MASK,
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0);
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if (ret)
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return ret;
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}
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/* Enable Interrupt output INT_OE in CFG3 register */
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if (phy_interrupt_is_valid(phydev)) {
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val = phy_read(phydev, DP83867_CFG3);
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