drm/i915: GuC-specific firmware loader
This fetches the required firmware image from the filesystem,
then loads it into the GuC's memory via a dedicated DMA engine.
This patch is derived from GuC loading work originally done by
Vinit Azad and Ben Widawsky.
v2:
Various improvements per review comments by Chris Wilson
v3:
Removed 'wait' parameter to intel_guc_ucode_load() as firmware
prefetch is no longer supported in the common firmware loader,
per Daniel Vetter's request.
Firmware checker callback fn now returns errno rather than bool.
v4:
Squash uC-independent code into GuC-specifc loader [Daniel Vetter]
Don't keep the driver working (by falling back to execlist mode)
if GuC firmware loading fails [Daniel Vetter]
v5:
Clarify WOPCM-related #defines [Tom O'Rourke]
Delete obsolete code no longer required with current h/w & f/w
[Tom O'Rourke]
Move the call to intel_guc_ucode_init() later, so that it can
allocate GEM objects, and have it fetch the firmware; then
intel_guc_ucode_load() doesn't need to fetch it later.
[Daniel Vetter].
v6:
Update comment describing intel_guc_ucode_load() [Tom O'Rourke]
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Alex Dai
Daniel Vetter
parent
04a60f9ffa
commit
33a732f407
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@ -40,6 +40,9 @@ i915-y += i915_cmd_parser.o \
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intel_ringbuffer.o \
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intel_uncore.o
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# general-purpose microcontroller (GuC) support
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i915-y += intel_guc_loader.o
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# autogenerated null render state
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i915-y += intel_renderstate_gen6.o \
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intel_renderstate_gen7.o \
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@ -435,6 +435,11 @@ static int i915_load_modeset_init(struct drm_device *dev)
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* working irqs for e.g. gmbus and dp aux transfers. */
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intel_modeset_init(dev);
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/* intel_guc_ucode_init() needs the mutex to allocate GEM objects */
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mutex_lock(&dev->struct_mutex);
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intel_guc_ucode_init(dev);
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mutex_unlock(&dev->struct_mutex);
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ret = i915_gem_init(dev);
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if (ret)
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goto cleanup_irq;
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@ -476,6 +481,9 @@ cleanup_gem:
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i915_gem_context_fini(dev);
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mutex_unlock(&dev->struct_mutex);
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cleanup_irq:
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mutex_lock(&dev->struct_mutex);
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intel_guc_ucode_fini(dev);
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mutex_unlock(&dev->struct_mutex);
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drm_irq_uninstall(dev);
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cleanup_gem_stolen:
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i915_gem_cleanup_stolen(dev);
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@ -1128,6 +1136,7 @@ int i915_driver_unload(struct drm_device *dev)
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flush_workqueue(dev_priv->wq);
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mutex_lock(&dev->struct_mutex);
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intel_guc_ucode_fini(dev);
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i915_gem_cleanup_ringbuffer(dev);
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i915_gem_context_fini(dev);
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mutex_unlock(&dev->struct_mutex);
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@ -50,6 +50,7 @@
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include "intel_guc.h"
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/* General customization:
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*/
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@ -1709,6 +1710,8 @@ struct drm_i915_private {
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struct i915_virtual_gpu vgpu;
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struct intel_guc guc;
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struct intel_csr csr;
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/* Display CSR-related protection */
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@ -1953,6 +1956,11 @@ static inline struct drm_i915_private *dev_to_i915(struct device *dev)
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return to_i915(dev_get_drvdata(dev));
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}
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static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
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{
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return container_of(guc, struct drm_i915_private, guc);
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}
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/* Iterate over initialised rings */
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#define for_each_ring(ring__, dev_priv__, i__) \
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for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
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@ -2557,6 +2565,9 @@ struct drm_i915_cmd_table {
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#define HAS_CSR(dev) (IS_SKYLAKE(dev))
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#define HAS_GUC_UCODE(dev) (IS_GEN9(dev))
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#define HAS_GUC_SCHED(dev) (IS_GEN9(dev))
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#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
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INTEL_INFO(dev)->gen >= 8)
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@ -4681,6 +4681,22 @@ i915_gem_init_hw(struct drm_device *dev)
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goto out;
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}
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/* We can't enable contexts until all firmware is loaded */
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ret = intel_guc_ucode_load(dev);
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if (ret) {
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/*
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* If we got an error and GuC submission is enabled, map
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* the error to -EIO so the GPU will be declared wedged.
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* OTOH, if we didn't intend to use the GuC anyway, just
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* discard the error and carry on.
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*/
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DRM_ERROR("Failed to initialize GuC, error %d%s\n", ret,
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i915.enable_guc_submission ? "" : " (ignored)");
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ret = i915.enable_guc_submission ? -EIO : 0;
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if (ret)
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goto out;
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}
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/* Now it is safe to go back round and do everything else: */
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for_each_ring(ring, dev_priv, i) {
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struct drm_i915_gem_request *req;
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@ -38,10 +38,6 @@
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#define GS_MIA_SHIFT 16
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#define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
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#define GUC_WOPCM_SIZE 0xc050
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#define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */
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#define GUC_WOPCM_OFFSET 0x80000 /* 512KB */
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#define SOFT_SCRATCH(n) (0xc180 + ((n) * 4))
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#define UOS_RSA_SCRATCH_0 0xc200
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@ -56,10 +52,18 @@
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#define UOS_MOVE (1<<4)
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#define START_DMA (1<<0)
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#define DMA_GUC_WOPCM_OFFSET 0xc340
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#define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
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#define GUC_WOPCM_SIZE 0xc050
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#define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */
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/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
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#define GUC_WOPCM_TOP (GUC_WOPCM_SIZE_VALUE)
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#define GEN8_GT_PM_CONFIG 0x138140
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#define GEN9LP_GT_PM_CONFIG 0x138140
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#define GEN9_GT_PM_CONFIG 0x13816c
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#define GEN8_GT_DOORBELL_ENABLE (1<<0)
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#define GT_DOORBELL_ENABLE (1<<0)
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#define GEN8_GTCR 0x4274
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#define GEN8_GTCR_INVALIDATE (1<<0)
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@ -80,7 +84,8 @@
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GUC_ENABLE_READ_CACHE_LOGIC | \
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GUC_ENABLE_MIA_CACHING | \
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GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | \
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GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA)
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GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | \
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GUC_ENABLE_MIA_CLOCK_GATING)
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#define HOST2GUC_INTERRUPT 0xc4c8
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#define HOST2GUC_TRIGGER (1<<0)
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@ -6860,7 +6860,9 @@ enum skl_disp_power_wells {
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#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
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#define GEN7_MISCCPCTL (0x9424)
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#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
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#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
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#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2)
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#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
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#define GEN8_GARBCNTL 0xB004
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#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
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@ -0,0 +1,67 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_GUC_H_
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#define _INTEL_GUC_H_
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#include "intel_guc_fwif.h"
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#include "i915_guc_reg.h"
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enum intel_guc_fw_status {
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GUC_FIRMWARE_FAIL = -1,
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GUC_FIRMWARE_NONE = 0,
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GUC_FIRMWARE_PENDING,
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GUC_FIRMWARE_SUCCESS
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};
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/*
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* This structure encapsulates all the data needed during the process
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* of fetching, caching, and loading the firmware image into the GuC.
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*/
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struct intel_guc_fw {
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struct drm_device * guc_dev;
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const char * guc_fw_path;
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size_t guc_fw_size;
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struct drm_i915_gem_object * guc_fw_obj;
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enum intel_guc_fw_status guc_fw_fetch_status;
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enum intel_guc_fw_status guc_fw_load_status;
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uint16_t guc_fw_major_wanted;
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uint16_t guc_fw_minor_wanted;
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uint16_t guc_fw_major_found;
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uint16_t guc_fw_minor_found;
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};
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struct intel_guc {
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struct intel_guc_fw guc_fw;
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uint32_t log_flags;
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};
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/* intel_guc_loader.c */
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extern void intel_guc_ucode_init(struct drm_device *dev);
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extern int intel_guc_ucode_load(struct drm_device *dev);
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extern void intel_guc_ucode_fini(struct drm_device *dev);
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extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
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#endif
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@ -32,9 +32,8 @@
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* EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST.
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*/
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#define GFXCORE_FAMILY_GEN8 11
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#define GFXCORE_FAMILY_GEN9 12
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#define GFXCORE_FAMILY_FORCE_ULONG 0x7fffffff
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#define GFXCORE_FAMILY_UNKNOWN 0x7fffffff
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#define GUC_CTX_PRIORITY_CRITICAL 0
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#define GUC_CTX_PRIORITY_HIGH 1
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@ -0,0 +1,529 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Vinit Azad <vinit.azad@intel.com>
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* Ben Widawsky <ben@bwidawsk.net>
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* Dave Gordon <david.s.gordon@intel.com>
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* Alex Dai <yu.dai@intel.com>
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*/
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#include <linux/firmware.h>
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#include "i915_drv.h"
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#include "intel_guc.h"
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/**
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* DOC: GuC
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*
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* intel_guc:
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* Top level structure of guc. It handles firmware loading and manages client
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* pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
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* ExecList submission.
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*
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* Firmware versioning:
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* The firmware build process will generate a version header file with major and
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* minor version defined. The versions are built into CSS header of firmware.
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* i915 kernel driver set the minimal firmware version required per platform.
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* The firmware installation package will install (symbolic link) proper version
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* of firmware.
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*
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* GuC address space:
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* GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
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* which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
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* 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
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* used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
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*
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* Firmware log:
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* Firmware log is enabled by setting i915.guc_log_level to non-negative level.
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* Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
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* i915_guc_load_status will print out firmware loading status and scratch
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* registers value.
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*
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*/
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#define I915_SKL_GUC_UCODE "i915/skl_guc_ver3.bin"
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MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
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/* User-friendly representation of an enum */
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const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
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{
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switch (status) {
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case GUC_FIRMWARE_FAIL:
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return "FAIL";
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case GUC_FIRMWARE_NONE:
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return "NONE";
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case GUC_FIRMWARE_PENDING:
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return "PENDING";
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case GUC_FIRMWARE_SUCCESS:
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return "SUCCESS";
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default:
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return "UNKNOWN!";
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}
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};
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static u32 get_gttype(struct drm_i915_private *dev_priv)
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{
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/* XXX: GT type based on PCI device ID? field seems unused by fw */
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return 0;
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}
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static u32 get_core_family(struct drm_i915_private *dev_priv)
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{
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switch (INTEL_INFO(dev_priv)->gen) {
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case 9:
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return GFXCORE_FAMILY_GEN9;
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default:
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DRM_ERROR("GUC: unsupported core family\n");
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return GFXCORE_FAMILY_UNKNOWN;
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}
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}
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static void set_guc_init_params(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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u32 params[GUC_CTL_MAX_DWORDS];
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int i;
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memset(¶ms, 0, sizeof(params));
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params[GUC_CTL_DEVICE_INFO] |=
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(get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
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(get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
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/*
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* GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
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* second. This ARAR is calculated by:
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* Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
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*/
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params[GUC_CTL_ARAT_HIGH] = 0;
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params[GUC_CTL_ARAT_LOW] = 100000000;
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params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
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params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
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GUC_CTL_VCS2_ENABLED;
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if (i915.guc_log_level >= 0) {
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params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
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params[GUC_CTL_DEBUG] =
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i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
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}
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I915_WRITE(SOFT_SCRATCH(0), 0);
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for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
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I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
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}
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/*
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* Read the GuC status register (GUC_STATUS) and store it in the
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* specified location; then return a boolean indicating whether
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* the value matches either of two values representing completion
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* of the GuC boot process.
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*
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* This is used for polling the GuC status in a wait_for_atomic()
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* loop below.
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*/
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static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
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u32 *status)
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{
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u32 val = I915_READ(GUC_STATUS);
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*status = val;
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return ((val & GS_UKERNEL_MASK) == GS_UKERNEL_READY ||
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(val & GS_UKERNEL_MASK) == GS_UKERNEL_LAPIC_DONE);
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}
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/*
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* Transfer the firmware image to RAM for execution by the microcontroller.
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*
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* GuC Firmware layout:
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* +-------------------------------+ ----
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* | CSS header | 128B
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* | contains major/minor version |
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* +-------------------------------+ ----
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* | uCode |
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* +-------------------------------+ ----
|
||||
* | RSA signature | 256B
|
||||
* +-------------------------------+ ----
|
||||
* | RSA public Key | 256B
|
||||
* +-------------------------------+ ----
|
||||
* | Public key modulus | 4B
|
||||
* +-------------------------------+ ----
|
||||
*
|
||||
* Architecturally, the DMA engine is bidirectional, and can potentially even
|
||||
* transfer between GTT locations. This functionality is left out of the API
|
||||
* for now as there is no need for it.
|
||||
*
|
||||
* Note that GuC needs the CSS header plus uKernel code to be copied by the
|
||||
* DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
|
||||
*/
|
||||
|
||||
#define UOS_CSS_HEADER_OFFSET 0
|
||||
#define UOS_VER_MINOR_OFFSET 0x44
|
||||
#define UOS_VER_MAJOR_OFFSET 0x46
|
||||
#define UOS_CSS_HEADER_SIZE 0x80
|
||||
#define UOS_RSA_SIG_SIZE 0x100
|
||||
#define UOS_CSS_SIGNING_SIZE 0x204
|
||||
|
||||
static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
|
||||
struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
|
||||
unsigned long offset;
|
||||
struct sg_table *sg = fw_obj->pages;
|
||||
u32 status, ucode_size, rsa[UOS_RSA_SIG_SIZE / sizeof(u32)];
|
||||
int i, ret = 0;
|
||||
|
||||
/* uCode size, also is where RSA signature starts */
|
||||
offset = ucode_size = guc_fw->guc_fw_size - UOS_CSS_SIGNING_SIZE;
|
||||
I915_WRITE(DMA_COPY_SIZE, ucode_size);
|
||||
|
||||
/* Copy RSA signature from the fw image to HW for verification */
|
||||
sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset);
|
||||
for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++)
|
||||
I915_WRITE(UOS_RSA_SCRATCH_0 + i * sizeof(u32), rsa[i]);
|
||||
|
||||
/* Set the source address for the new blob */
|
||||
offset = i915_gem_obj_ggtt_offset(fw_obj);
|
||||
I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
|
||||
I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
|
||||
|
||||
/*
|
||||
* Set the DMA destination. Current uCode expects the code to be
|
||||
* loaded at 8k; locations below this are used for the stack.
|
||||
*/
|
||||
I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
|
||||
I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
|
||||
|
||||
/* Finally start the DMA */
|
||||
I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
|
||||
|
||||
/*
|
||||
* Spin-wait for the DMA to complete & the GuC to start up.
|
||||
* NB: Docs recommend not using the interrupt for completion.
|
||||
* Measurements indicate this should take no more than 20ms, so a
|
||||
* timeout here indicates that the GuC has failed and is unusable.
|
||||
* (Higher levels of the driver will attempt to fall back to
|
||||
* execlist mode if this happens.)
|
||||
*/
|
||||
ret = wait_for_atomic(guc_ucode_response(dev_priv, &status), 100);
|
||||
|
||||
DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
|
||||
I915_READ(DMA_CTRL), status);
|
||||
|
||||
if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
|
||||
DRM_ERROR("GuC firmware signature verification failed\n");
|
||||
ret = -ENOEXEC;
|
||||
}
|
||||
|
||||
DRM_DEBUG_DRIVER("returning %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Load the GuC firmware blob into the MinuteIA.
|
||||
*/
|
||||
static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
|
||||
struct drm_device *dev = dev_priv->dev;
|
||||
int ret;
|
||||
|
||||
ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
|
||||
if (ret) {
|
||||
DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
|
||||
if (ret) {
|
||||
DRM_DEBUG_DRIVER("pin failed %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
|
||||
I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
|
||||
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
|
||||
/* init WOPCM */
|
||||
I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
|
||||
I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
|
||||
|
||||
/* Enable MIA caching. GuC clock gating is disabled. */
|
||||
I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
|
||||
|
||||
/* WaC6DisallowByGfxPause*/
|
||||
I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
|
||||
|
||||
if (IS_BROXTON(dev))
|
||||
I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
|
||||
else
|
||||
I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
|
||||
|
||||
if (IS_GEN9(dev)) {
|
||||
/* DOP Clock Gating Enable for GuC clocks */
|
||||
I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
|
||||
I915_READ(GEN7_MISCCPCTL)));
|
||||
|
||||
/* allows for 5us before GT can go to RC6 */
|
||||
I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
|
||||
}
|
||||
|
||||
set_guc_init_params(dev_priv);
|
||||
|
||||
ret = guc_ucode_xfer_dma(dev_priv);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
|
||||
/*
|
||||
* We keep the object pages for reuse during resume. But we can unpin it
|
||||
* now that DMA has completed, so it doesn't continue to take up space.
|
||||
*/
|
||||
i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_guc_ucode_load() - load GuC uCode into the device
|
||||
* @dev: drm device
|
||||
*
|
||||
* Called from gem_init_hw() during driver loading and also after a GPU reset.
|
||||
*
|
||||
* The firmware image should have already been fetched into memory by the
|
||||
* earlier call to intel_guc_ucode_init(), so here we need only check that
|
||||
* is succeeded, and then transfer the image to the h/w.
|
||||
*
|
||||
* Return: non-zero code on error
|
||||
*/
|
||||
int intel_guc_ucode_load(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
|
||||
int err = 0;
|
||||
|
||||
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
|
||||
intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
|
||||
intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
|
||||
|
||||
if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
|
||||
return 0;
|
||||
|
||||
if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
|
||||
guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
|
||||
return -ENOEXEC;
|
||||
|
||||
guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
|
||||
|
||||
DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
|
||||
intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
|
||||
|
||||
switch (guc_fw->guc_fw_fetch_status) {
|
||||
case GUC_FIRMWARE_FAIL:
|
||||
/* something went wrong :( */
|
||||
err = -EIO;
|
||||
goto fail;
|
||||
|
||||
case GUC_FIRMWARE_NONE:
|
||||
case GUC_FIRMWARE_PENDING:
|
||||
default:
|
||||
/* "can't happen" */
|
||||
WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
|
||||
guc_fw->guc_fw_path,
|
||||
intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
|
||||
guc_fw->guc_fw_fetch_status);
|
||||
err = -ENXIO;
|
||||
goto fail;
|
||||
|
||||
case GUC_FIRMWARE_SUCCESS:
|
||||
break;
|
||||
}
|
||||
|
||||
err = guc_ucode_xfer(dev_priv);
|
||||
if (err)
|
||||
goto fail;
|
||||
|
||||
guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
|
||||
|
||||
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
|
||||
intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
|
||||
intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
|
||||
guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
|
||||
{
|
||||
struct drm_i915_gem_object *obj;
|
||||
const struct firmware *fw;
|
||||
const u8 *css_header;
|
||||
const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_CSS_SIGNING_SIZE;
|
||||
const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_CSS_SIGNING_SIZE
|
||||
- 0x8000; /* 32k reserved (8K stack + 24k context) */
|
||||
int err;
|
||||
|
||||
DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
|
||||
intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
|
||||
|
||||
err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
|
||||
if (err)
|
||||
goto fail;
|
||||
if (!fw)
|
||||
goto fail;
|
||||
|
||||
DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
|
||||
guc_fw->guc_fw_path, fw);
|
||||
DRM_DEBUG_DRIVER("firmware file size %zu (minimum %zu, maximum %zu)\n",
|
||||
fw->size, minsize, maxsize);
|
||||
|
||||
/* Check the size of the blob befoe examining buffer contents */
|
||||
if (fw->size < minsize || fw->size > maxsize)
|
||||
goto fail;
|
||||
|
||||
/*
|
||||
* The GuC firmware image has the version number embedded at a well-known
|
||||
* offset within the firmware blob; note that major / minor version are
|
||||
* TWO bytes each (i.e. u16), although all pointers and offsets are defined
|
||||
* in terms of bytes (u8).
|
||||
*/
|
||||
css_header = fw->data + UOS_CSS_HEADER_OFFSET;
|
||||
guc_fw->guc_fw_major_found = *(u16 *)(css_header + UOS_VER_MAJOR_OFFSET);
|
||||
guc_fw->guc_fw_minor_found = *(u16 *)(css_header + UOS_VER_MINOR_OFFSET);
|
||||
|
||||
if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
|
||||
guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
|
||||
DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
|
||||
guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
|
||||
guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
|
||||
err = -ENOEXEC;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
|
||||
guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
|
||||
guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
|
||||
|
||||
obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
|
||||
if (IS_ERR_OR_NULL(obj)) {
|
||||
err = obj ? PTR_ERR(obj) : -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
guc_fw->guc_fw_obj = obj;
|
||||
guc_fw->guc_fw_size = fw->size;
|
||||
|
||||
DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
|
||||
guc_fw->guc_fw_obj);
|
||||
|
||||
release_firmware(fw);
|
||||
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
|
||||
return;
|
||||
|
||||
fail:
|
||||
DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
|
||||
err, fw, guc_fw->guc_fw_obj);
|
||||
DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
|
||||
guc_fw->guc_fw_path, err);
|
||||
|
||||
obj = guc_fw->guc_fw_obj;
|
||||
if (obj)
|
||||
drm_gem_object_unreference(&obj->base);
|
||||
guc_fw->guc_fw_obj = NULL;
|
||||
|
||||
release_firmware(fw); /* OK even if fw is NULL */
|
||||
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_guc_ucode_init() - define parameters and fetch firmware
|
||||
* @dev: drm device
|
||||
*
|
||||
* Called early during driver load, but after GEM is initialised.
|
||||
* The device struct_mutex must be held by the caller, as we're
|
||||
* going to allocate a GEM object to hold the firmware image.
|
||||
*
|
||||
* The firmware will be transferred to the GuC's memory later,
|
||||
* when intel_guc_ucode_load() is called.
|
||||
*/
|
||||
void intel_guc_ucode_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
|
||||
const char *fw_path;
|
||||
|
||||
if (!HAS_GUC_SCHED(dev))
|
||||
i915.enable_guc_submission = false;
|
||||
|
||||
if (!HAS_GUC_UCODE(dev)) {
|
||||
fw_path = NULL;
|
||||
} else if (IS_SKYLAKE(dev)) {
|
||||
fw_path = I915_SKL_GUC_UCODE;
|
||||
guc_fw->guc_fw_major_wanted = 3;
|
||||
guc_fw->guc_fw_minor_wanted = 0;
|
||||
} else {
|
||||
i915.enable_guc_submission = false;
|
||||
fw_path = ""; /* unknown device */
|
||||
}
|
||||
|
||||
guc_fw->guc_dev = dev;
|
||||
guc_fw->guc_fw_path = fw_path;
|
||||
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
|
||||
guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
|
||||
|
||||
if (fw_path == NULL)
|
||||
return;
|
||||
|
||||
if (*fw_path == '\0') {
|
||||
DRM_ERROR("No GuC firmware known for this platform\n");
|
||||
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
|
||||
return;
|
||||
}
|
||||
|
||||
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
|
||||
DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
|
||||
guc_fw_fetch(dev, guc_fw);
|
||||
/* status must now be FAIL or SUCCESS */
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_guc_ucode_fini() - clean up all allocated resources
|
||||
* @dev: drm device
|
||||
*/
|
||||
void intel_guc_ucode_fini(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
|
||||
|
||||
if (guc_fw->guc_fw_obj)
|
||||
drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
|
||||
guc_fw->guc_fw_obj = NULL;
|
||||
|
||||
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
|
||||
}
|
||||
Loading…
Reference in New Issue