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[PATCH] ide: fix HPT3xx hotswap support
Fix the broken hotswap code: on HPT37x it caused RESET- to glitch when tristating the bus (the MISC control 3/6 and soft control 2 need to be written to in the certain order), and for HPT36x the obsolete HDIO_TRISTATE_HWIF ioctl() handler was called instead which treated the state argument wrong. Also, get rid of the soft control reg. 1 wtite to enable IDE interrupt -- this is done in init_hpt37x() already... Have been tested on HPT370 and 371N. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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parent
471a0bda5a
commit
33b18a6025
1 changed files with 36 additions and 79 deletions
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@ -70,6 +70,8 @@
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* - fix/remove bad/unused timing tables and use one set of tables for the whole
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* HPT37x chip family; save space by introducing the separate transfer mode
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* table in which the mode lookup is done
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* - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
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* and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
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* <source@mvista.com>
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*
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*/
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@ -914,101 +916,68 @@ static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
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hpt3xxn_set_clock(hwif, wantclock);
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}
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/*
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* Since SUN Cobalt is attempting to do this operation, I should disclose
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* this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
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* HOTSWAP ATA Infrastructure.
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*/
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static void hpt3xx_reset (ide_drive_t *drive)
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{
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}
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static int hpt3xx_tristate (ide_drive_t * drive, int state)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u8 reg59h = 0, reset = (hwif->channel) ? 0x80 : 0x40;
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u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
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pci_read_config_byte(dev, 0x59, ®59h);
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pci_read_config_byte(dev, state_reg, ®XXh);
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if (state) {
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(void) ide_do_reset(drive);
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pci_write_config_byte(dev, state_reg, regXXh|0x80);
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pci_write_config_byte(dev, 0x59, reg59h|reset);
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} else {
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pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
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pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
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(void) ide_do_reset(drive);
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}
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return 0;
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}
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/*
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* set/get power state for a drive.
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* turning the power off does the following things:
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* 1) soft-reset the drive
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* 2) tri-states the ide bus
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* Set/get power state for a drive.
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*
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* when we turn things back on, we need to re-initialize things.
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* When we turn the power back on, we need to re-initialize things.
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*/
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#define TRISTATE_BIT 0x8000
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static int hpt370_busproc(ide_drive_t * drive, int state)
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static int hpt3xx_busproc(ide_drive_t *drive, int state)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *dev = hwif->pci_dev;
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u8 tristate = 0, resetmask = 0, bus_reg = 0;
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u16 tri_reg;
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u8 tristate, resetmask, bus_reg = 0;
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u16 tri_reg = 0;
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hwif->bus_state = state;
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if (hwif->channel) {
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/* secondary channel */
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tristate = 0x56;
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resetmask = 0x80;
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tristate = 0x56;
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resetmask = 0x80;
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} else {
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/* primary channel */
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tristate = 0x52;
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tristate = 0x52;
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resetmask = 0x40;
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}
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/* grab status */
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/* Grab the status. */
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pci_read_config_word(dev, tristate, &tri_reg);
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pci_read_config_byte(dev, 0x59, &bus_reg);
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/* set the state. we don't set it if we don't need to do so.
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* make sure that the drive knows that it has failed if it's off */
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/*
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* Set the state. We don't set it if we don't need to do so.
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* Make sure that the drive knows that it has failed if it's off.
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*/
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switch (state) {
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case BUSSTATE_ON:
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hwif->drives[0].failures = 0;
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hwif->drives[1].failures = 0;
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if ((bus_reg & resetmask) == 0)
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if (!(bus_reg & resetmask))
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return 0;
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tri_reg &= ~TRISTATE_BIT;
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bus_reg &= ~resetmask;
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break;
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hwif->drives[0].failures = hwif->drives[1].failures = 0;
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pci_write_config_byte(dev, 0x59, bus_reg & ~resetmask);
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pci_write_config_word(dev, tristate, tri_reg & ~TRISTATE_BIT);
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return 0;
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case BUSSTATE_OFF:
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hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
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hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
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if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
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if ((bus_reg & resetmask) && !(tri_reg & TRISTATE_BIT))
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return 0;
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tri_reg &= ~TRISTATE_BIT;
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bus_reg |= resetmask;
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break;
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case BUSSTATE_TRISTATE:
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hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
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hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
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if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
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if ((bus_reg & resetmask) && (tri_reg & TRISTATE_BIT))
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return 0;
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tri_reg |= TRISTATE_BIT;
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bus_reg |= resetmask;
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break;
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default:
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return -EINVAL;
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}
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pci_write_config_byte(dev, 0x59, bus_reg);
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pci_write_config_word(dev, tristate, tri_reg);
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hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
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hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
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pci_write_config_word(dev, tristate, tri_reg);
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pci_write_config_byte(dev, 0x59, bus_reg | resetmask);
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return 0;
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}
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@ -1306,23 +1275,11 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
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if (serialize && hwif->mate)
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hwif->serialized = hwif->mate->serialized = 1;
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if (info->revision >= 3) {
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u8 reg5ah = 0;
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pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
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/*
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* set up ioctl for power status.
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* note: power affects both
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* drives on each channel
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*/
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hwif->resetproc = &hpt3xx_reset;
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hwif->busproc = &hpt370_busproc;
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} else if (info->revision >= 2) {
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hwif->resetproc = &hpt3xx_reset;
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hwif->busproc = &hpt3xx_tristate;
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} else {
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hwif->resetproc = &hpt3xx_reset;
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hwif->busproc = &hpt3xx_tristate;
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}
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/*
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* Set up ioctl for power status.
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* NOTE: power affects both drives on each channel.
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*/
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hwif->busproc = &hpt3xx_busproc;
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if (!hwif->dma_base) {
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hwif->drives[0].autotune = 1;
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