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drm/amdgpu: remove more of the ring backup code
Not used anymore. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
bb06d7ef99
commit
33b7ed0122
7 changed files with 4 additions and 101 deletions
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@ -776,8 +776,6 @@ struct amdgpu_ring {
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struct amdgpu_bo *ring_obj;
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volatile uint32_t *ring;
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unsigned rptr_offs;
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u64 next_rptr_gpu_addr;
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volatile u32 *next_rptr_cpu_addr;
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unsigned wptr;
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unsigned wptr_old;
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unsigned ring_size;
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@ -796,7 +794,6 @@ struct amdgpu_ring {
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u32 doorbell_index;
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bool use_doorbell;
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unsigned wptr_offs;
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unsigned next_rptr_offs;
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unsigned fence_offs;
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uint64_t current_ctx;
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enum amdgpu_ring_type type;
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@ -190,14 +190,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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return r;
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}
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r = amdgpu_wb_get(adev, &ring->next_rptr_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring next_rptr wb alloc failed\n", r);
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return r;
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}
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ring->next_rptr_gpu_addr = adev->wb.gpu_addr + ring->next_rptr_offs * 4;
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ring->next_rptr_cpu_addr = &adev->wb.wb[ring->next_rptr_offs];
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r = amdgpu_wb_get(adev, &ring->cond_exe_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
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@ -280,7 +272,6 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
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amdgpu_wb_free(ring->adev, ring->fence_offs);
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amdgpu_wb_free(ring->adev, ring->rptr_offs);
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amdgpu_wb_free(ring->adev, ring->wptr_offs);
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amdgpu_wb_free(ring->adev, ring->next_rptr_offs);
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if (ring_obj) {
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r = amdgpu_bo_reserve(ring_obj, false);
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@ -224,17 +224,6 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
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unsigned vm_id, bool ctx_switch)
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{
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u32 extra_bits = vm_id & 0xf;
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u32 next_rptr = ring->wptr + 5;
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while ((next_rptr & 7) != 4)
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next_rptr++;
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next_rptr += 4;
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amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
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amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
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amdgpu_ring_write(ring, 1); /* number of DWs to follow */
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amdgpu_ring_write(ring, next_rptr);
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/* IB packet must end on a 8 DW boundary */
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cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
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@ -2056,17 +2056,6 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
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unsigned vm_id, bool ctx_switch)
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{
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u32 header, control = 0;
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u32 next_rptr = ring->wptr + 5;
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if (ctx_switch)
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next_rptr += 2;
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next_rptr += 4;
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amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
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amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
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amdgpu_ring_write(ring, next_rptr);
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/* insert SWITCH_BUFFER packet before first IB in the ring frame */
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if (ctx_switch) {
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@ -2095,22 +2084,9 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
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struct amdgpu_ib *ib,
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unsigned vm_id, bool ctx_switch)
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{
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u32 header, control = 0;
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u32 next_rptr = ring->wptr + 5;
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u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
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control |= INDIRECT_BUFFER_VALID;
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next_rptr += 4;
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amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
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amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
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amdgpu_ring_write(ring, next_rptr);
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header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
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control |= ib->length_dw | (vm_id << 24);
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amdgpu_ring_write(ring, header);
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amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
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amdgpu_ring_write(ring,
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#ifdef __BIG_ENDIAN
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(2 << 0) |
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@ -5929,17 +5929,6 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
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unsigned vm_id, bool ctx_switch)
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{
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u32 header, control = 0;
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u32 next_rptr = ring->wptr + 5;
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if (ctx_switch)
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next_rptr += 2;
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next_rptr += 4;
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amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
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amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
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amdgpu_ring_write(ring, next_rptr);
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/* insert SWITCH_BUFFER packet before first IB in the ring frame */
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if (ctx_switch) {
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@ -5968,23 +5957,9 @@ static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
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struct amdgpu_ib *ib,
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unsigned vm_id, bool ctx_switch)
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{
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u32 header, control = 0;
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u32 next_rptr = ring->wptr + 5;
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u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
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control |= INDIRECT_BUFFER_VALID;
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next_rptr += 4;
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amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
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amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
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amdgpu_ring_write(ring, next_rptr);
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header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
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control |= ib->length_dw | (vm_id << 24);
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amdgpu_ring_write(ring, header);
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amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
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amdgpu_ring_write(ring,
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#ifdef __BIG_ENDIAN
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(2 << 0) |
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@ -255,19 +255,6 @@ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
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unsigned vm_id, bool ctx_switch)
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{
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u32 vmid = vm_id & 0xf;
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u32 next_rptr = ring->wptr + 5;
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while ((next_rptr & 7) != 2)
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next_rptr++;
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next_rptr += 6;
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amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
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SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
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amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
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amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
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amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
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amdgpu_ring_write(ring, next_rptr);
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/* IB packet must end on a 8 DW boundary */
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sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
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@ -415,18 +415,6 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
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unsigned vm_id, bool ctx_switch)
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{
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u32 vmid = vm_id & 0xf;
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u32 next_rptr = ring->wptr + 5;
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while ((next_rptr & 7) != 2)
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next_rptr++;
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next_rptr += 6;
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amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
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SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
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amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
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amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
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amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
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amdgpu_ring_write(ring, next_rptr);
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/* IB packet must end on a 8 DW boundary */
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sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
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