mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 19:00:25 +00:00
drm/nouveau/pci: merge agp handling from nouveau drm
This commit reinstates the pre-DEVINIT AGP fiddling that was broken in an earlier commit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
26c9e8effe
commit
340b0e7c50
18 changed files with 271 additions and 239 deletions
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@ -18,7 +18,6 @@ nouveau-y += $(nvkm-y)
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ifdef CONFIG_X86
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nouveau-$(CONFIG_ACPI) += nouveau_acpi.o
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endif
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nouveau-y += nouveau_agp.o
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nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o
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nouveau-y += nouveau_drm.o
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nouveau-y += nouveau_hwmon.o
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@ -45,6 +45,7 @@ u64 nvif_device_time(struct nvif_device *);
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#include <subdev/i2c.h>
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#include <subdev/timer.h>
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#include <subdev/therm.h>
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#include <subdev/pci.h>
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#define nvxx_device(a) ({ \
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struct nvif_device *_device = (a); \
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@ -24,6 +24,7 @@
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#include <linux/power_supply.h>
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include <linux/agp_backend.h>
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#include <asm/unaligned.h>
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@ -4,6 +4,7 @@
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const char *nvkm_stropt(const char *optstr, const char *opt, int *len);
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bool nvkm_boolopt(const char *optstr, const char *opt, bool value);
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long nvkm_longopt(const char *optstr, const char *opt, long value);
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int nvkm_dbgopt(const char *optstr, const char *sub);
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/* compares unterminated string 'str' with zero-terminated string 'cmp' */
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@ -7,6 +7,17 @@ struct nvkm_pci {
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struct nvkm_subdev subdev;
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struct pci_dev *pdev;
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int irq;
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struct {
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struct agp_bridge_data *bridge;
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u32 mode;
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u64 base;
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u64 size;
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int mtrr;
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bool cma;
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bool acquired;
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} agp;
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bool msi;
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};
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@ -498,7 +498,7 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS)
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args.start += chan->ntfy_vma.offset;
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args.limit += chan->ntfy_vma.offset;
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} else
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if (drm->agp.stat == ENABLED) {
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if (drm->agp.bridge) {
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args.target = NV_DMA_V0_TARGET_AGP;
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args.access = NV_DMA_V0_ACCESS_RDWR;
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args.start += drm->agp.base + chan->ntfy->bo.offset;
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@ -1,198 +0,0 @@
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#include <linux/module.h>
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#include "nouveau_drm.h"
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#include "nouveau_agp.h"
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#include "nouveau_reg.h"
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#include <core/pci.h>
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#if __OS_HAS_AGP
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MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
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static int nouveau_agpmode = -1;
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module_param_named(agpmode, nouveau_agpmode, int, 0400);
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struct nouveau_agpmode_quirk {
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u16 hostbridge_vendor;
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u16 hostbridge_device;
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u16 chip_vendor;
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u16 chip_device;
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int mode;
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};
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static struct nouveau_agpmode_quirk nouveau_agpmode_quirk_list[] = {
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/* VIA Apollo PRO133x / GeForce FX 5600 Ultra, max agpmode 2, fdo #20341 */
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{ PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_NVIDIA, 0x0311, 2 },
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{},
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};
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static unsigned long
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get_agp_mode(struct nouveau_drm *drm, const struct drm_agp_info *info)
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{
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struct nvif_device *device = &drm->device;
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struct pci_dev *pdev = nvxx_device(device)->func->pci(nvxx_device(device))->pdev;
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struct nouveau_agpmode_quirk *quirk = nouveau_agpmode_quirk_list;
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int agpmode = nouveau_agpmode;
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unsigned long mode = info->mode;
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/*
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* FW seems to be broken on nv18, it makes the card lock up
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* randomly.
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*/
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if (device->info.chipset == 0x18)
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mode &= ~PCI_AGP_COMMAND_FW;
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/*
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* Go through the quirks list and adjust the agpmode accordingly.
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*/
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while (agpmode == -1 && quirk->hostbridge_vendor) {
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if (info->id_vendor == quirk->hostbridge_vendor &&
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info->id_device == quirk->hostbridge_device &&
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pdev->vendor == quirk->chip_vendor &&
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pdev->device == quirk->chip_device) {
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agpmode = quirk->mode;
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NV_INFO(drm, "Forcing agp mode to %dX. Use agpmode to override.\n",
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agpmode);
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break;
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}
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++quirk;
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}
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/*
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* AGP mode set in the command line.
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*/
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if (agpmode > 0) {
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bool agpv3 = mode & 0x8;
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int rate = agpv3 ? agpmode / 4 : agpmode;
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mode = (mode & ~0x7) | (rate & 0x7);
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}
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return mode;
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}
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static bool
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nouveau_agp_enabled(struct nouveau_drm *drm)
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{
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struct drm_device *dev = drm->dev;
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if (!dev->pdev || !drm_pci_device_is_agp(dev) || !dev->agp)
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return false;
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if (drm->agp.stat == UNKNOWN) {
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if (!nouveau_agpmode)
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return false;
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#ifdef __powerpc__
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/* Disable AGP by default on all PowerPC machines for
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* now -- At least some UniNorth-2 AGP bridges are
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* known to be broken: DMA from the host to the card
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* works just fine, but writeback from the card to the
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* host goes straight to memory untranslated bypassing
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* the GATT somehow, making them quite painful to deal
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* with...
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*/
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if (nouveau_agpmode == -1)
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return false;
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#endif
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return true;
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}
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return (drm->agp.stat == ENABLED);
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}
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#endif
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void
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nouveau_agp_reset(struct nouveau_drm *drm)
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{
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#if __OS_HAS_AGP
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struct nvif_object *device = &drm->device.object;
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struct drm_device *dev = drm->dev;
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u32 save[2];
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int ret;
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if (!nouveau_agp_enabled(drm))
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return;
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/* First of all, disable fast writes, otherwise if it's
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* already enabled in the AGP bridge and we disable the card's
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* AGP controller we might be locking ourselves out of it. */
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if ((nvif_rd32(device, NV04_PBUS_PCI_NV_19) |
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dev->agp->mode) & PCI_AGP_COMMAND_FW) {
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struct drm_agp_info info;
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struct drm_agp_mode mode;
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ret = drm_agp_info(dev, &info);
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if (ret)
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return;
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mode.mode = get_agp_mode(drm, &info);
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mode.mode &= ~PCI_AGP_COMMAND_FW;
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ret = drm_agp_enable(dev, mode);
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if (ret)
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return;
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}
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/* clear busmaster bit, and disable AGP */
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save[0] = nvif_mask(device, NV04_PBUS_PCI_NV_1, 0x00000004, 0x00000000);
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nvif_wr32(device, NV04_PBUS_PCI_NV_19, 0);
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/* reset PGRAPH, PFIFO and PTIMER */
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save[1] = nvif_mask(device, 0x000200, 0x00011100, 0x00000000);
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nvif_mask(device, 0x000200, 0x00011100, save[1]);
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/* and restore bustmaster bit (gives effect of resetting AGP) */
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nvif_wr32(device, NV04_PBUS_PCI_NV_1, save[0]);
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#endif
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}
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void
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nouveau_agp_init(struct nouveau_drm *drm)
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{
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#if __OS_HAS_AGP
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struct drm_device *dev = drm->dev;
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struct drm_agp_info info;
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struct drm_agp_mode mode;
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int ret;
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if (!nouveau_agp_enabled(drm))
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return;
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drm->agp.stat = DISABLE;
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ret = drm_agp_acquire(dev);
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if (ret) {
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NV_ERROR(drm, "unable to acquire AGP: %d\n", ret);
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return;
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}
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ret = drm_agp_info(dev, &info);
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if (ret) {
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NV_ERROR(drm, "unable to get AGP info: %d\n", ret);
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return;
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}
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/* see agp.h for the AGPSTAT_* modes available */
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mode.mode = get_agp_mode(drm, &info);
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ret = drm_agp_enable(dev, mode);
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if (ret) {
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NV_ERROR(drm, "unable to enable AGP: %d\n", ret);
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return;
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}
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drm->agp.stat = ENABLED;
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drm->agp.base = info.aperture_base;
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drm->agp.size = info.aperture_size;
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#endif
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}
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void
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nouveau_agp_fini(struct nouveau_drm *drm)
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{
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#if __OS_HAS_AGP
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struct drm_device *dev = drm->dev;
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if (dev->agp && dev->agp->acquired)
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drm_agp_release(dev);
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#endif
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}
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@ -1,10 +0,0 @@
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#ifndef __NOUVEAU_AGP_H__
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#define __NOUVEAU_AGP_H__
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struct nouveau_drm;
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void nouveau_agp_reset(struct nouveau_drm *);
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void nouveau_agp_init(struct nouveau_drm *);
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void nouveau_agp_fini(struct nouveau_drm *);
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#endif
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@ -576,10 +576,9 @@ nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
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{
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#if __OS_HAS_AGP
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struct nouveau_drm *drm = nouveau_bdev(bdev);
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struct drm_device *dev = drm->dev;
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if (drm->agp.stat == ENABLED) {
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return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
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if (drm->agp.bridge) {
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return ttm_agp_tt_create(bdev, drm->agp.bridge, size,
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page_flags, dummy_read);
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}
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#endif
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@ -631,12 +630,12 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
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if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA)
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man->func = &nouveau_gart_manager;
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else
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if (drm->agp.stat != ENABLED)
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if (!drm->agp.bridge)
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man->func = &nv04_gart_manager;
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else
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man->func = &ttm_bo_manager_func;
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if (drm->agp.stat == ENABLED) {
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if (drm->agp.bridge) {
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_WC;
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@ -1368,10 +1367,10 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
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return 0;
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case TTM_PL_TT:
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#if __OS_HAS_AGP
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if (drm->agp.stat == ENABLED) {
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if (drm->agp.bridge) {
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mem->bus.offset = mem->start << PAGE_SHIFT;
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mem->bus.base = drm->agp.base;
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mem->bus.is_iomem = !drm->dev->agp->cant_use_aperture;
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mem->bus.is_iomem = !drm->agp.cma;
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}
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#endif
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if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype)
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@ -1498,7 +1497,7 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm)
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return ttm_dma_populate(ttm_dma, dev->dev);
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#if __OS_HAS_AGP
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if (drm->agp.stat == ENABLED) {
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if (drm->agp.bridge) {
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return ttm_agp_tt_populate(ttm);
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}
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#endif
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@ -1565,7 +1564,7 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
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}
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#if __OS_HAS_AGP
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if (drm->agp.stat == ENABLED) {
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if (drm->agp.bridge) {
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ttm_agp_tt_unpopulate(ttm);
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return;
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}
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@ -160,7 +160,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
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args.limit = device->info.ram_user - 1;
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}
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} else {
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if (chan->drm->agp.stat == ENABLED) {
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if (chan->drm->agp.bridge) {
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args.target = NV_DMA_V0_TARGET_AGP;
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args.access = NV_DMA_V0_ACCESS_RDWR;
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args.start = chan->drm->agp.base;
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@ -328,7 +328,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
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args.start = 0;
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args.limit = cli->vm->mmu->limit - 1;
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} else
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if (chan->drm->agp.stat == ENABLED) {
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if (chan->drm->agp.bridge) {
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args.target = NV_DMA_V0_TARGET_AGP;
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args.access = NV_DMA_V0_ACCESS_RDWR;
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args.start = chan->drm->agp.base;
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@ -41,7 +41,6 @@
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#include "nouveau_dma.h"
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#include "nouveau_ttm.h"
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#include "nouveau_gem.h"
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#include "nouveau_agp.h"
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#include "nouveau_vga.h"
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#include "nouveau_sysfs.h"
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#include "nouveau_hwmon.h"
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@ -423,7 +422,6 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
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nvif_mask(&drm->device.object, 0x00088080, 0x00000800, 0x00000000);
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nouveau_vga_init(drm);
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nouveau_agp_init(drm);
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if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
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ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
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@ -474,7 +472,6 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
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fail_bios:
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nouveau_ttm_fini(drm);
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fail_ttm:
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nouveau_agp_fini(drm);
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nouveau_vga_fini(drm);
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fail_device:
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nvif_device_fini(&drm->device);
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@ -500,7 +497,6 @@ nouveau_drm_unload(struct drm_device *dev)
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nouveau_bios_takedown(dev);
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nouveau_ttm_fini(drm);
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nouveau_agp_fini(drm);
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nouveau_vga_fini(drm);
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nvif_device_fini(&drm->device);
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@ -584,7 +580,6 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime)
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if (ret)
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goto fail_client;
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nouveau_agp_fini(drm);
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return 0;
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fail_client:
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@ -609,13 +604,8 @@ nouveau_do_resume(struct drm_device *dev, bool runtime)
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nouveau_cli *cli;
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NV_INFO(drm, "re-enabling device...\n");
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nouveau_agp_reset(drm);
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NV_INFO(drm, "resuming kernel object tree...\n");
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nvif_client_resume(&drm->client.base);
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nouveau_agp_init(drm);
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NV_INFO(drm, "resuming client object trees...\n");
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if (drm->fence && nouveau_fence(drm)->resume)
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@ -929,7 +919,6 @@ nouveau_driver_fops = {
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static struct drm_driver
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driver_stub = {
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.driver_features =
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DRIVER_USE_AGP |
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DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER |
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DRIVER_KMS_LEGACY_CONTEXT,
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|
|
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@ -111,13 +111,10 @@ struct nouveau_drm {
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struct list_head clients;
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struct {
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enum {
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UNKNOWN = 0,
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DISABLE = 1,
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ENABLED = 2
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} stat;
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struct agp_bridge_data *bridge;
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u32 base;
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u32 size;
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bool cma;
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} agp;
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/* TTM interface support */
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||||
|
|
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@ -336,13 +336,21 @@ int
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nouveau_ttm_init(struct nouveau_drm *drm)
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{
|
||||
struct nvkm_device *device = nvxx_device(&drm->device);
|
||||
struct nvkm_pci *pci = device->pci;
|
||||
struct drm_device *dev = drm->dev;
|
||||
u32 bits;
|
||||
int ret;
|
||||
|
||||
if (pci && pci->agp.bridge) {
|
||||
drm->agp.bridge = pci->agp.bridge;
|
||||
drm->agp.base = pci->agp.base;
|
||||
drm->agp.size = pci->agp.size;
|
||||
drm->agp.cma = pci->agp.cma;
|
||||
}
|
||||
|
||||
bits = nvxx_mmu(&drm->device)->dma_bits;
|
||||
if (nvxx_device(&drm->device)->func->pci) {
|
||||
if (drm->agp.stat == ENABLED ||
|
||||
if (drm->agp.bridge ||
|
||||
!pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
|
||||
bits = 32;
|
||||
|
||||
|
|
@ -386,7 +394,7 @@ nouveau_ttm_init(struct nouveau_drm *drm)
|
|||
device->func->resource_size(device, 1));
|
||||
|
||||
/* GART init */
|
||||
if (drm->agp.stat != ENABLED) {
|
||||
if (!drm->agp.bridge) {
|
||||
drm->gem.gart_available = nvxx_mmu(&drm->device)->limit;
|
||||
} else {
|
||||
drm->gem.gart_available = drm->agp.size;
|
||||
|
|
|
|||
|
|
@ -73,6 +73,24 @@ nvkm_boolopt(const char *optstr, const char *opt, bool value)
|
|||
return value;
|
||||
}
|
||||
|
||||
long
|
||||
nvkm_longopt(const char *optstr, const char *opt, long value)
|
||||
{
|
||||
long result = value;
|
||||
int arglen;
|
||||
char *s;
|
||||
|
||||
optstr = nvkm_stropt(optstr, opt, &arglen);
|
||||
if (optstr && (s = kstrndup(optstr, arglen, GFP_KERNEL))) {
|
||||
int ret = kstrtol(s, 0, &value);
|
||||
if (ret == 0)
|
||||
result = value;
|
||||
kfree(s);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int
|
||||
nvkm_dbgopt(const char *optstr, const char *sub)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
nvkm-y += nvkm/subdev/pci/agp.o
|
||||
nvkm-y += nvkm/subdev/pci/base.o
|
||||
nvkm-y += nvkm/subdev/pci/nv04.o
|
||||
nvkm-y += nvkm/subdev/pci/nv40.o
|
||||
|
|
|
|||
171
drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c
Normal file
171
drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c
Normal file
|
|
@ -0,0 +1,171 @@
|
|||
/*
|
||||
* Copyright 2015 Nouveau Project
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include "agp.h"
|
||||
#ifdef __NVKM_PCI_AGP_H__
|
||||
#include <core/option.h>
|
||||
|
||||
struct nvkm_device_agp_quirk {
|
||||
u16 hostbridge_vendor;
|
||||
u16 hostbridge_device;
|
||||
u16 chip_vendor;
|
||||
u16 chip_device;
|
||||
int mode;
|
||||
};
|
||||
|
||||
static const struct nvkm_device_agp_quirk
|
||||
nvkm_device_agp_quirks[] = {
|
||||
/* VIA Apollo PRO133x / GeForce FX 5600 Ultra - fdo#20341 */
|
||||
{ PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_NVIDIA, 0x0311, 2 },
|
||||
{},
|
||||
};
|
||||
|
||||
void
|
||||
nvkm_agp_fini(struct nvkm_pci *pci)
|
||||
{
|
||||
if (pci->agp.acquired) {
|
||||
agp_backend_release(pci->agp.bridge);
|
||||
pci->agp.acquired = false;
|
||||
}
|
||||
}
|
||||
|
||||
/* Ensure AGP controller is in a consistent state in case we need to
|
||||
* execute the VBIOS DEVINIT scripts.
|
||||
*/
|
||||
void
|
||||
nvkm_agp_preinit(struct nvkm_pci *pci)
|
||||
{
|
||||
struct nvkm_device *device = pci->subdev.device;
|
||||
u32 mode = nvkm_pci_rd32(pci, 0x004c);
|
||||
u32 save[2];
|
||||
|
||||
/* First of all, disable fast writes, otherwise if it's already
|
||||
* enabled in the AGP bridge and we disable the card's AGP
|
||||
* controller we might be locking ourselves out of it.
|
||||
*/
|
||||
if ((mode | pci->agp.mode) & PCI_AGP_COMMAND_FW) {
|
||||
mode = pci->agp.mode & ~PCI_AGP_COMMAND_FW;
|
||||
agp_enable(pci->agp.bridge, mode);
|
||||
}
|
||||
|
||||
/* clear busmaster bit, and disable AGP */
|
||||
save[0] = nvkm_pci_rd32(pci, 0x0004);
|
||||
nvkm_pci_wr32(pci, 0x0004, save[0] & ~0x00000004);
|
||||
nvkm_pci_wr32(pci, 0x004c, 0x00000000);
|
||||
|
||||
/* reset PGRAPH, PFIFO and PTIMER */
|
||||
save[1] = nvkm_mask(device, 0x000200, 0x00011100, 0x00000000);
|
||||
nvkm_mask(device, 0x000200, 0x00011100, save[1]);
|
||||
|
||||
/* and restore busmaster bit (gives effect of resetting AGP) */
|
||||
nvkm_pci_wr32(pci, 0x0004, save[0]);
|
||||
}
|
||||
|
||||
int
|
||||
nvkm_agp_init(struct nvkm_pci *pci)
|
||||
{
|
||||
if (!agp_backend_acquire(pci->pdev)) {
|
||||
nvkm_error(&pci->subdev, "failed to acquire agp\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
agp_enable(pci->agp.bridge, pci->agp.mode);
|
||||
pci->agp.acquired = true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
nvkm_agp_dtor(struct nvkm_pci *pci)
|
||||
{
|
||||
arch_phys_wc_del(pci->agp.mtrr);
|
||||
}
|
||||
|
||||
void
|
||||
nvkm_agp_ctor(struct nvkm_pci *pci)
|
||||
{
|
||||
const struct nvkm_device_agp_quirk *quirk = nvkm_device_agp_quirks;
|
||||
struct nvkm_subdev *subdev = &pci->subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
struct agp_kern_info info;
|
||||
int mode = -1;
|
||||
|
||||
#ifdef __powerpc__
|
||||
/* Disable AGP by default on all PowerPC machines for now -- At
|
||||
* least some UniNorth-2 AGP bridges are known to be broken:
|
||||
* DMA from the host to the card works just fine, but writeback
|
||||
* from the card to the host goes straight to memory
|
||||
* untranslated bypassing that GATT somehow, making them quite
|
||||
* painful to deal with...
|
||||
*/
|
||||
mode = 0;
|
||||
#endif
|
||||
mode = nvkm_longopt(device->cfgopt, "NvAGP", mode);
|
||||
|
||||
/* acquire bridge temporarily, so that we can copy its info */
|
||||
if (!(pci->agp.bridge = agp_backend_acquire(pci->pdev))) {
|
||||
nvkm_warn(subdev, "failed to acquire agp\n");
|
||||
return;
|
||||
}
|
||||
agp_copy_info(pci->agp.bridge, &info);
|
||||
agp_backend_release(pci->agp.bridge);
|
||||
|
||||
pci->agp.mode = info.mode;
|
||||
pci->agp.base = info.aper_base;
|
||||
pci->agp.size = info.aper_size * 1024 * 1024;
|
||||
pci->agp.cma = info.cant_use_aperture;
|
||||
pci->agp.mtrr = -1;
|
||||
|
||||
/* determine if bridge + chipset combination needs a workaround */
|
||||
while (quirk->hostbridge_vendor) {
|
||||
if (info.device->vendor == quirk->hostbridge_vendor &&
|
||||
info.device->device == quirk->hostbridge_device &&
|
||||
pci->pdev->vendor == quirk->chip_vendor &&
|
||||
pci->pdev->device == quirk->chip_device) {
|
||||
nvkm_info(subdev, "forcing default agp mode to %dX, "
|
||||
"use NvAGP=<mode> to override\n",
|
||||
quirk->mode);
|
||||
mode = quirk->mode;
|
||||
break;
|
||||
}
|
||||
quirk++;
|
||||
}
|
||||
|
||||
/* apply quirk / user-specified mode */
|
||||
if (mode >= 1) {
|
||||
if (pci->agp.mode & 0x00000008)
|
||||
mode /= 4; /* AGPv3 */
|
||||
pci->agp.mode &= ~0x00000007;
|
||||
pci->agp.mode |= (mode & 0x7);
|
||||
} else
|
||||
if (mode == 0) {
|
||||
pci->agp.bridge = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
/* fast writes appear to be broken on nv18, they make the card
|
||||
* lock up randomly.
|
||||
*/
|
||||
if (device->chipset == 0x18)
|
||||
pci->agp.mode &= ~PCI_AGP_COMMAND_FW;
|
||||
|
||||
pci->agp.mtrr = arch_phys_wc_add(pci->agp.base, pci->agp.size);
|
||||
}
|
||||
#endif
|
||||
18
drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.h
Normal file
18
drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.h
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
#include "priv.h"
|
||||
#if defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE))
|
||||
#ifndef __NVKM_PCI_AGP_H__
|
||||
#define __NVKM_PCI_AGP_H__
|
||||
|
||||
void nvkm_agp_ctor(struct nvkm_pci *);
|
||||
void nvkm_agp_dtor(struct nvkm_pci *);
|
||||
void nvkm_agp_preinit(struct nvkm_pci *);
|
||||
int nvkm_agp_init(struct nvkm_pci *);
|
||||
void nvkm_agp_fini(struct nvkm_pci *);
|
||||
#endif
|
||||
#else
|
||||
static inline void nvkm_agp_ctor(struct nvkm_pci *pci) {}
|
||||
static inline void nvkm_agp_dtor(struct nvkm_pci *pci) {}
|
||||
static inline void nvkm_agp_preinit(struct nvkm_pci *pci) {}
|
||||
static inline int nvkm_agp_init(struct nvkm_pci *pci) { return -ENOSYS; }
|
||||
static inline void nvkm_agp_fini(struct nvkm_pci *pci) {}
|
||||
#endif
|
||||
|
|
@ -22,6 +22,7 @@
|
|||
* Authors: Ben Skeggs <bskeggs@redhat.com>
|
||||
*/
|
||||
#include "priv.h"
|
||||
#include "agp.h"
|
||||
|
||||
#include <core/option.h>
|
||||
#include <core/pci.h>
|
||||
|
|
@ -76,10 +77,24 @@ static int
|
|||
nvkm_pci_fini(struct nvkm_subdev *subdev, bool suspend)
|
||||
{
|
||||
struct nvkm_pci *pci = nvkm_pci(subdev);
|
||||
|
||||
if (pci->irq >= 0) {
|
||||
free_irq(pci->irq, pci);
|
||||
pci->irq = -1;
|
||||
};
|
||||
|
||||
if (pci->agp.bridge)
|
||||
nvkm_agp_fini(pci);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nvkm_pci_preinit(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nvkm_pci *pci = nvkm_pci(subdev);
|
||||
if (pci->agp.bridge)
|
||||
nvkm_agp_preinit(pci);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -90,6 +105,12 @@ nvkm_pci_init(struct nvkm_subdev *subdev)
|
|||
struct pci_dev *pdev = pci->pdev;
|
||||
int ret;
|
||||
|
||||
if (pci->agp.bridge) {
|
||||
ret = nvkm_agp_init(pci);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = request_irq(pdev->irq, nvkm_pci_intr, IRQF_SHARED, "nvkm", pci);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -102,6 +123,7 @@ static void *
|
|||
nvkm_pci_dtor(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nvkm_pci *pci = nvkm_pci(subdev);
|
||||
nvkm_agp_dtor(pci);
|
||||
if (pci->msi)
|
||||
pci_disable_msi(pci->pdev);
|
||||
return nvkm_pci(subdev);
|
||||
|
|
@ -110,6 +132,7 @@ nvkm_pci_dtor(struct nvkm_subdev *subdev)
|
|||
static const struct nvkm_subdev_func
|
||||
nvkm_pci_func = {
|
||||
.dtor = nvkm_pci_dtor,
|
||||
.preinit = nvkm_pci_preinit,
|
||||
.init = nvkm_pci_init,
|
||||
.fini = nvkm_pci_fini,
|
||||
};
|
||||
|
|
@ -127,6 +150,9 @@ nvkm_pci_new_(const struct nvkm_pci_func *func, struct nvkm_device *device,
|
|||
pci->pdev = device->func->pci(device)->pdev;
|
||||
pci->irq = -1;
|
||||
|
||||
if (device->type == NVKM_DEVICE_AGP)
|
||||
nvkm_agp_ctor(pci);
|
||||
|
||||
switch (pci->pdev->device & 0x0ff0) {
|
||||
case 0x00f0:
|
||||
case 0x02e0:
|
||||
|
|
|
|||
Loading…
Reference in a new issue