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drm/amdgpu: add an implement for check_power_state equal for Si.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 52 additions and 0 deletions
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@ -7957,6 +7957,57 @@ static int si_dpm_early_init(void *handle)
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return 0;
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}
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static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
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const struct rv7xx_pl *si_cpl2)
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{
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return ((si_cpl1->mclk == si_cpl2->mclk) &&
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(si_cpl1->sclk == si_cpl2->sclk) &&
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(si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
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(si_cpl1->vddc == si_cpl2->vddc) &&
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(si_cpl1->vddci == si_cpl2->vddci));
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}
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static int si_check_state_equal(struct amdgpu_device *adev,
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struct amdgpu_ps *cps,
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struct amdgpu_ps *rps,
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bool *equal)
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{
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struct si_ps *si_cps;
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struct si_ps *si_rps;
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int i;
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if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
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return -EINVAL;
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si_cps = si_get_ps(cps);
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si_rps = si_get_ps(rps);
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if (si_cps == NULL) {
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printk("si_cps is NULL\n");
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*equal = false;
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return 0;
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}
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if (si_cps->performance_level_count != si_rps->performance_level_count) {
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*equal = false;
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return 0;
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}
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for (i = 0; i < si_cps->performance_level_count; i++) {
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if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
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&(si_rps->performance_levels[i]))) {
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*equal = false;
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return 0;
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}
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}
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/* If all performance levels are the same try to use the UVD clocks to break the tie.*/
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*equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
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*equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
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return 0;
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}
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const struct amd_ip_funcs si_dpm_ip_funcs = {
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.name = "si_dpm",
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@ -7991,6 +8042,7 @@ static const struct amdgpu_dpm_funcs si_dpm_funcs = {
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.get_fan_control_mode = &si_dpm_get_fan_control_mode,
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.set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
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.get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
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.check_state_equal = &si_check_state_equal,
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.get_vce_clock_state = amdgpu_get_vce_clock_state,
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};
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