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ARM i.MX avic: convert to use generic irq chip
Convert i.MX avic irq handler to use generic irq chip. This not only provides a cleanup implementation of irq chip handler, but also implements suspend/resume interface with the help of generic irq chip interface. Change mxc_irq_chip to a new structure mxc_extra_irq to handle fiq and priority functions. Signed-off-by: Hui Wang <jason77.wang@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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parent
40d97b89bd
commit
3439a397a8
4 changed files with 75 additions and 36 deletions
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@ -50,6 +50,8 @@
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void __iomem *avic_base;
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static u32 avic_saved_mask_reg[2];
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#ifdef CONFIG_MXC_IRQ_PRIOR
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static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
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{
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@ -90,24 +92,8 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
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}
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#endif /* CONFIG_FIQ */
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/* Disable interrupt number "irq" in the AVIC */
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static void mxc_mask_irq(struct irq_data *d)
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{
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__raw_writel(d->irq, avic_base + AVIC_INTDISNUM);
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}
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/* Enable interrupt number "irq" in the AVIC */
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static void mxc_unmask_irq(struct irq_data *d)
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{
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__raw_writel(d->irq, avic_base + AVIC_INTENNUM);
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}
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static struct mxc_irq_chip mxc_avic_chip = {
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.base = {
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.irq_ack = mxc_mask_irq,
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.irq_mask = mxc_mask_irq,
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.irq_unmask = mxc_unmask_irq,
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},
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static struct mxc_extra_irq avic_extra_irq = {
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#ifdef CONFIG_MXC_IRQ_PRIOR
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.set_priority = avic_irq_set_priority,
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#endif
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@ -116,6 +102,56 @@ static struct mxc_irq_chip mxc_avic_chip = {
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#endif
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};
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#ifdef CONFIG_PM
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static void avic_irq_suspend(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = gc->chip_types;
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int idx = gc->irq_base >> 5;
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avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
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__raw_writel(gc->wake_active, avic_base + ct->regs.mask);
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}
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static void avic_irq_resume(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = gc->chip_types;
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int idx = gc->irq_base >> 5;
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__raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
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}
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#else
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#define avic_irq_suspend NULL
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#define avic_irq_resume NULL
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#endif
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static __init void avic_init_gc(unsigned int irq_start)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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int idx = irq_start >> 5;
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gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
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handle_level_irq);
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gc->private = &avic_extra_irq;
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gc->wake_enabled = IRQ_MSK(32);
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_ack = irq_gc_mask_clr_bit;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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ct->chip.irq_suspend = avic_irq_suspend;
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ct->chip.irq_resume = avic_irq_resume;
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ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
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ct->regs.ack = ct->regs.mask;
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irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
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}
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/*
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* This function initializes the AVIC hardware and disables all the
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* interrupts. It registers the interrupt enable and disable functions
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@ -140,11 +176,9 @@ void __init mxc_init_irq(void __iomem *irqbase)
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/* all IRQ no FIQ */
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__raw_writel(0, avic_base + AVIC_INTTYPEH);
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__raw_writel(0, avic_base + AVIC_INTTYPEL);
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for (i = 0; i < AVIC_NUM_IRQS; i++) {
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irq_set_chip_and_handler(i, &mxc_avic_chip.base,
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handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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for (i = 0; i < AVIC_NUM_IRQS; i += 32)
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avic_init_gc(i);
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/* Set default priority value (0) for all IRQ's */
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for (i = 0; i < 8; i++)
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@ -157,4 +191,3 @@ void __init mxc_init_irq(void __iomem *irqbase)
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printk(KERN_INFO "MXC IRQ initialized\n");
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}
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@ -23,17 +23,17 @@
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int imx_irq_set_priority(unsigned char irq, unsigned char prio)
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{
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struct mxc_irq_chip *chip;
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struct irq_chip *base;
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struct irq_chip_generic *gc;
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struct mxc_extra_irq *exirq;
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int ret;
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ret = -ENOSYS;
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base = irq_get_chip(irq);
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if (base) {
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chip = container_of(base, struct mxc_irq_chip, base);
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if (chip->set_priority)
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ret = chip->set_priority(irq, prio);
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gc = irq_get_chip_data(irq);
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if (gc && gc->private) {
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exirq = gc->private;
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if (exirq->set_priority)
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ret = exirq->set_priority(irq, prio);
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}
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return ret;
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@ -43,15 +43,16 @@ EXPORT_SYMBOL(imx_irq_set_priority);
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int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
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{
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struct irq_chip_generic *gc;
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int (*set_irq_fiq)(unsigned int, unsigned int);
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struct mxc_extra_irq *exirq;
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int ret;
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ret = -ENOSYS;
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gc = irq_get_chip_data(irq);
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if (gc && gc->private) {
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set_irq_fiq = gc->private;
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ret = set_irq_fiq(irq, type);
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exirq = gc->private;
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if (exirq->set_irq_fiq)
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ret = exirq->set_irq_fiq(irq, type);
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}
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return ret;
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@ -19,9 +19,8 @@
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#ifndef __PLAT_MXC_IRQ_COMMON_H__
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#define __PLAT_MXC_IRQ_COMMON_H__
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struct mxc_irq_chip
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struct mxc_extra_irq
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{
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struct irq_chip base;
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int (*set_priority)(unsigned char irq, unsigned char prio);
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int (*set_irq_fiq)(unsigned int irq, unsigned int type);
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};
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@ -74,6 +74,12 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
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static unsigned int *wakeup_intr[4];
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static struct mxc_extra_irq tzic_extra_irq = {
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#ifdef CONFIG_FIQ
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.set_irq_fiq = tzic_set_irq_fiq,
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#endif
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};
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static __init void tzic_init_gc(unsigned int irq_start)
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{
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struct irq_chip_generic *gc;
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@ -82,7 +88,7 @@ static __init void tzic_init_gc(unsigned int irq_start)
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gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
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handle_level_irq);
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gc->private = tzic_set_irq_fiq;
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gc->private = &tzic_extra_irq;
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gc->wake_enabled = IRQ_MSK(32);
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wakeup_intr[idx] = &gc->wake_active;
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