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arm: mvebu: Add IPI support via doorbells
This patch enhances the IRQ controller driver to add support for Inter-Processor-Interrupts that are needed to enable SMP support. Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit is contained in:
parent
7444dad240
commit
344e873e56
4 changed files with 103 additions and 10 deletions
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@ -6,9 +6,15 @@ Required properties:
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- interrupt-controller: Identifies the node as an interrupt controller.
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- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
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The cell is the IRQ number
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- reg: Should contain PMIC registers location and length. First pair
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for the main interrupt registers, second pair for the per-CPU
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interrupt registers
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interrupt registers. For this last pair, to be compliant with SMP
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support, the "virtual" must be use (For the record, these registers
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automatically map to the interrupt controller registers of the
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current CPU)
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Example:
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@ -18,6 +24,6 @@ Example:
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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reg = <0xd0020000 0x1000>,
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<0xd0021000 0x1000>;
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reg = <0xd0020a00 0x1d0>,
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<0xd0021070 0x58>;
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};
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@ -24,7 +24,7 @@ / {
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mpic: interrupt-controller@d0020000 {
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reg = <0xd0020a00 0x1d0>,
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<0xd0021870 0x58>;
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<0xd0021070 0x58>;
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};
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armada-370-xp-pmsu@d0022000 {
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@ -19,4 +19,11 @@
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#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000)
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#define ARMADA_370_XP_REGS_SIZE SZ_1M
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#ifdef CONFIG_SMP
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#include <linux/cpumask.h>
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void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq);
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void armada_xp_mpic_smp_cpu_init(void);
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#endif
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#endif /* __MACH_ARMADA_370_XP_H */
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@ -24,6 +24,7 @@
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#include <linux/irqdomain.h>
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#include <asm/mach/arch.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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/* Interrupt Controller Registers Map */
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#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
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@ -35,6 +36,12 @@
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#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
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#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
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#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
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#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
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#define ACTIVE_DOORBELLS (8)
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static void __iomem *per_cpu_int_base;
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static void __iomem *main_int_base;
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static struct irq_domain *armada_370_xp_mpic_domain;
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@ -51,11 +58,22 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
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per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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#ifdef CONFIG_SMP
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static int armada_xp_set_affinity(struct irq_data *d,
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const struct cpumask *mask_val, bool force)
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{
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return 0;
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}
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#endif
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static struct irq_chip armada_370_xp_irq_chip = {
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.name = "armada_370_xp_irq",
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.irq_mask = armada_370_xp_irq_mask,
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.irq_mask_ack = armada_370_xp_irq_mask,
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.irq_unmask = armada_370_xp_irq_unmask,
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#ifdef CONFIG_SMP
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.irq_set_affinity = armada_xp_set_affinity,
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#endif
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};
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static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
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@ -72,6 +90,41 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
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return 0;
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}
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#ifdef CONFIG_SMP
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void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
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{
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int cpu;
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unsigned long map = 0;
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/* Convert our logical CPU mask into a physical one. */
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for_each_cpu(cpu, mask)
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map |= 1 << cpu_logical_map(cpu);
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/*
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* Ensure that stores to Normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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dsb();
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/* submit softirq */
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writel((map << 8) | irq, main_int_base +
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ARMADA_370_XP_SW_TRIG_INT_OFFS);
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}
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void armada_xp_mpic_smp_cpu_init(void)
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{
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/* Clear pending IPIs */
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writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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/* Enable first 8 IPIs */
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writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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/* Unmask IPI interrupt */
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writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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#endif /* CONFIG_SMP */
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static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
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.map = armada_370_xp_mpic_irq_map,
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.xlate = irq_domain_xlate_onecell,
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@ -98,6 +151,11 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
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panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
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irq_set_default_host(armada_370_xp_mpic_domain);
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#ifdef CONFIG_SMP
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armada_xp_mpic_smp_cpu_init();
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#endif
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return 0;
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}
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@ -111,14 +169,36 @@ asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
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ARMADA_370_XP_CPU_INTACK_OFFS);
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irqnr = irqstat & 0x3FF;
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if (irqnr < 1023) {
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irqnr =
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irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
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if (irqnr > 1022)
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break;
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if (irqnr >= 8) {
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irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
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irqnr);
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handle_IRQ(irqnr, regs);
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continue;
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}
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#ifdef CONFIG_SMP
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/* IPI Handling */
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if (irqnr == 0) {
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u32 ipimask, ipinr;
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ipimask = readl_relaxed(per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
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& 0xFF;
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writel(0x0, per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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/* Handle all pending doorbells */
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for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) {
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if (ipimask & (0x1 << ipinr))
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handle_IPI(ipinr, regs);
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}
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continue;
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}
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#endif
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break;
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} while (1);
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}
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