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spi/imx: use mx21 to name SPI_IMX_VER_0_0 function and macro
SPI_IMX_VER_0_0 covers i.mx21 and i.mx27. It makes more sense to use mx21 rather than mx27 to name SPI_IMX_VER_0_0 function and macro, since i.mx21 comes out ealier than i.mx27. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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parent
edd501bbf1
commit
3451fb1563
1 changed files with 31 additions and 31 deletions
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@ -406,70 +406,70 @@ static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx)
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readl(spi_imx->base + MXC_CSPIRXDATA);
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}
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#define MX27_INTREG_RR (1 << 4)
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#define MX27_INTREG_TEEN (1 << 9)
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#define MX27_INTREG_RREN (1 << 13)
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#define MX21_INTREG_RR (1 << 4)
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#define MX21_INTREG_TEEN (1 << 9)
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#define MX21_INTREG_RREN (1 << 13)
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#define MX27_CSPICTRL_POL (1 << 5)
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#define MX27_CSPICTRL_PHA (1 << 6)
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#define MX27_CSPICTRL_SSPOL (1 << 8)
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#define MX27_CSPICTRL_XCH (1 << 9)
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#define MX27_CSPICTRL_ENABLE (1 << 10)
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#define MX27_CSPICTRL_MASTER (1 << 11)
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#define MX27_CSPICTRL_DR_SHIFT 14
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#define MX27_CSPICTRL_CS_SHIFT 19
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#define MX21_CSPICTRL_POL (1 << 5)
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#define MX21_CSPICTRL_PHA (1 << 6)
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#define MX21_CSPICTRL_SSPOL (1 << 8)
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#define MX21_CSPICTRL_XCH (1 << 9)
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#define MX21_CSPICTRL_ENABLE (1 << 10)
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#define MX21_CSPICTRL_MASTER (1 << 11)
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#define MX21_CSPICTRL_DR_SHIFT 14
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#define MX21_CSPICTRL_CS_SHIFT 19
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static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
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static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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unsigned int val = 0;
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if (enable & MXC_INT_TE)
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val |= MX27_INTREG_TEEN;
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val |= MX21_INTREG_TEEN;
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if (enable & MXC_INT_RR)
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val |= MX27_INTREG_RREN;
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val |= MX21_INTREG_RREN;
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writel(val, spi_imx->base + MXC_CSPIINT);
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}
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static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx)
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static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
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{
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unsigned int reg;
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reg = readl(spi_imx->base + MXC_CSPICTRL);
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reg |= MX27_CSPICTRL_XCH;
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reg |= MX21_CSPICTRL_XCH;
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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}
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static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx,
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static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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{
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unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
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unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
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int cs = spi_imx->chipselect[config->cs];
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reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
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MX27_CSPICTRL_DR_SHIFT;
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MX21_CSPICTRL_DR_SHIFT;
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reg |= config->bpw - 1;
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if (config->mode & SPI_CPHA)
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reg |= MX27_CSPICTRL_PHA;
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reg |= MX21_CSPICTRL_PHA;
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if (config->mode & SPI_CPOL)
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reg |= MX27_CSPICTRL_POL;
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reg |= MX21_CSPICTRL_POL;
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if (config->mode & SPI_CS_HIGH)
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reg |= MX27_CSPICTRL_SSPOL;
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reg |= MX21_CSPICTRL_SSPOL;
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if (cs < 0)
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reg |= (cs + 32) << MX27_CSPICTRL_CS_SHIFT;
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reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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return 0;
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}
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static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx)
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static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
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{
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return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
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return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
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}
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static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx)
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static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
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{
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writel(1, spi_imx->base + MXC_RESET);
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}
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@ -552,11 +552,11 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] = {
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#endif
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#ifdef CONFIG_SPI_IMX_VER_0_0
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[SPI_IMX_VER_0_0] = {
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.intctrl = mx27_intctrl,
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.config = mx27_config,
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.trigger = mx27_trigger,
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.rx_available = mx27_rx_available,
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.reset = spi_imx0_0_reset,
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.intctrl = mx21_intctrl,
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.config = mx21_config,
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.trigger = mx21_trigger,
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.rx_available = mx21_rx_available,
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.reset = mx21_reset,
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.fifosize = 8,
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},
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#endif
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