From 2fe182dd2783c870cb21f20732ff62f9cbb2451a Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 28 Jun 2023 14:17:22 +0800 Subject: [PATCH 01/37] dt-bindings: clock: imx93: Add PDM IPG clk Add PDM IPG clk. Reviewed-by: Shengjiu Wang Signed-off-by: Chancel Liu Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230628061724.2056520-1-ping.bai@nxp.com Signed-off-by: Abel Vesa --- include/dt-bindings/clock/imx93-clock.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h index 35a1f62053a5..787c9e74dc96 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -203,6 +203,7 @@ #define IMX93_CLK_ARM_PLL 198 #define IMX93_CLK_A55_SEL 199 #define IMX93_CLK_A55_CORE 200 -#define IMX93_CLK_END 201 +#define IMX93_CLK_PDM_IPG 201 +#define IMX93_CLK_END 202 #endif From 3ea570486039a12bb9dcbec977c70390b3d3c902 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 28 Jun 2023 14:17:23 +0800 Subject: [PATCH 02/37] clk: imx93: Add PDM IPG clk The IPG clk and MCLK of PDM share the same control gate. Reviewed-by: Shengjiu Wang Signed-off-by: Chancel Liu Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/20230628061724.2056520-2-ping.bai@nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx93.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index b6c7c2725906..f5dc1ee4990d 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -32,6 +32,7 @@ static u32 share_count_sai1; static u32 share_count_sai2; static u32 share_count_sai3; static u32 share_count_mub; +static u32 share_count_pdm; static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"}; static const char *parent_names[MAX_SEL][4] = { @@ -236,7 +237,8 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, }, { IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, }, { IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "osc_24m", 0x9a80, }, - { IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, }, + { IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, 0, &share_count_pdm}, + { IMX93_CLK_PDM_IPG, "pdm_ipg_clk", "bus_aon_root", 0x9ac0, 0, &share_count_pdm}, { IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, }, { IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, }, { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, }, From 07ba6d1ae524c627ac55bb98d5610d4fc44d3fe7 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Wed, 28 Jun 2023 14:17:24 +0800 Subject: [PATCH 03/37] clk: imx: Add 519.75MHz frequency support for imx9 pll For video pll, it may need 519.75MHz clock frequency for the LVDS display usage. So add 519.75MHz frequency config support for video pll. Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/20230628061724.2056520-3-ping.bai@nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-fracn-gppll.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index c54f9999da04..44462ab50e51 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -81,6 +81,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6), PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6), + PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8), PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8), PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), From 2deed4cda3b76bcb8be2533f5bd07803b1bfa452 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Fri, 7 Jul 2023 22:02:48 +0200 Subject: [PATCH 04/37] clk: imx: clk-gpr-mux: Simplify .determine_rate() imx_clk_gpr_mux_determine_rate() is the same as __clk_mux_determine_rate(), so use the latter to save some LoC. Signed-off-by: Christophe JAILLET Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/ac8bd50c41b84f244bb0ec94e8aed25c513c9037.1688760152.git.christophe.jaillet@wanadoo.fr Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-gpr-mux.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/clk/imx/clk-gpr-mux.c b/drivers/clk/imx/clk-gpr-mux.c index 0b5a97698b47..0e14b61cba84 100644 --- a/drivers/clk/imx/clk-gpr-mux.c +++ b/drivers/clk/imx/clk-gpr-mux.c @@ -65,16 +65,10 @@ static int imx_clk_gpr_mux_set_parent(struct clk_hw *hw, u8 index) return regmap_update_bits(priv->regmap, priv->reg, priv->mask, val); } -static int imx_clk_gpr_mux_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - return clk_mux_determine_rate_flags(hw, req, 0); -} - static const struct clk_ops imx_clk_gpr_mux_ops = { .get_parent = imx_clk_gpr_mux_get_parent, .set_parent = imx_clk_gpr_mux_set_parent, - .determine_rate = imx_clk_gpr_mux_determine_rate, + .determine_rate = __clk_mux_determine_rate, }; struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible, From 94945b23133db0b698ffe764d8a82593906d1e74 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Wed, 5 Jul 2023 14:53:08 +0800 Subject: [PATCH 05/37] clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20230705065313.67043-8-frank.li@vivo.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8qxp-lpcg.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c index 5e31a6a24b3a..e0ee9a2572d0 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c @@ -183,7 +183,6 @@ static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev, unsigned int bit_offset[IMX_LPCG_MAX_CLKS]; struct clk_hw_onecell_data *clk_data; struct clk_hw **clk_hws; - struct resource *res; void __iomem *base; int count; int idx; @@ -193,8 +192,7 @@ static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev, if (!of_device_is_compatible(np, "fsl,imx8qxp-lpcg")) return -EINVAL; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); From a70cd8cdf7492006b547f46cc365eed79d331323 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 25 Jul 2023 12:56:23 +0800 Subject: [PATCH 06/37] dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support Add the clock dt-binding file for Audio Clock Mux. which is the IP for i.MX8QM, i.MX8QXP, i.MX8DXL. Add the clockid for clocks in header file. The Audio Clock Mux is binded with all the audio IP and audio clocks in the subsystem, so need to list the power domain of related clocks and IPs. Each clock and IP has a power domain, so there are so many power domains. Signed-off-by: Shengjiu Wang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1690260984-25744-2-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa --- .../bindings/clock/fsl,imx8-acm.yaml | 282 ++++++++++++++++++ include/dt-bindings/clock/imx8-clock.h | 28 ++ 2 files changed, 310 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml b/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml new file mode 100644 index 000000000000..07b9d21719c4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml @@ -0,0 +1,282 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8 Audio Clock Mux + +maintainers: + - Shengjiu Wang + +description: | + NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP + used to control Audio related clock on the SoC. + +properties: + compatible: + enum: + - fsl,imx8dxl-acm + - fsl,imx8qm-acm + - fsl,imx8qxp-acm + + reg: + maxItems: 1 + + power-domains: + minItems: 13 + maxItems: 21 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h + for the full list of i.MX8 ACM clock IDs. + + clocks: + minItems: 13 + maxItems: 27 + + clock-names: + minItems: 13 + maxItems: 27 + +required: + - compatible + - reg + - power-domains + - '#clock-cells' + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-acm + then: + properties: + power-domains: + items: + - description: power domain of IMX_SC_R_AUDIO_CLK_0 + - description: power domain of IMX_SC_R_AUDIO_CLK_1 + - description: power domain of IMX_SC_R_MCLK_OUT_0 + - description: power domain of IMX_SC_R_MCLK_OUT_1 + - description: power domain of IMX_SC_R_AUDIO_PLL_0 + - description: power domain of IMX_SC_R_AUDIO_PLL_1 + - description: power domain of IMX_SC_R_ASRC_0 + - description: power domain of IMX_SC_R_ASRC_1 + - description: power domain of IMX_SC_R_ESAI_0 + - description: power domain of IMX_SC_R_SAI_0 + - description: power domain of IMX_SC_R_SAI_1 + - description: power domain of IMX_SC_R_SAI_2 + - description: power domain of IMX_SC_R_SAI_3 + - description: power domain of IMX_SC_R_SAI_4 + - description: power domain of IMX_SC_R_SAI_5 + - description: power domain of IMX_SC_R_SPDIF_0 + - description: power domain of IMX_SC_R_MQS_0 + + clocks: + minItems: 18 + maxItems: 18 + + clock-names: + items: + - const: aud_rec_clk0_lpcg_clk + - const: aud_rec_clk1_lpcg_clk + - const: aud_pll_div_clk0_lpcg_clk + - const: aud_pll_div_clk1_lpcg_clk + - const: ext_aud_mclk0 + - const: ext_aud_mclk1 + - const: esai0_rx_clk + - const: esai0_rx_hf_clk + - const: esai0_tx_clk + - const: esai0_tx_hf_clk + - const: spdif0_rx + - const: sai0_rx_bclk + - const: sai0_tx_bclk + - const: sai1_rx_bclk + - const: sai1_tx_bclk + - const: sai2_rx_bclk + - const: sai3_rx_bclk + - const: sai4_rx_bclk + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-acm + then: + properties: + power-domains: + items: + - description: power domain of IMX_SC_R_AUDIO_CLK_0 + - description: power domain of IMX_SC_R_AUDIO_CLK_1 + - description: power domain of IMX_SC_R_MCLK_OUT_0 + - description: power domain of IMX_SC_R_MCLK_OUT_1 + - description: power domain of IMX_SC_R_AUDIO_PLL_0 + - description: power domain of IMX_SC_R_AUDIO_PLL_1 + - description: power domain of IMX_SC_R_ASRC_0 + - description: power domain of IMX_SC_R_ASRC_1 + - description: power domain of IMX_SC_R_ESAI_0 + - description: power domain of IMX_SC_R_ESAI_1 + - description: power domain of IMX_SC_R_SAI_0 + - description: power domain of IMX_SC_R_SAI_1 + - description: power domain of IMX_SC_R_SAI_2 + - description: power domain of IMX_SC_R_SAI_3 + - description: power domain of IMX_SC_R_SAI_4 + - description: power domain of IMX_SC_R_SAI_5 + - description: power domain of IMX_SC_R_SAI_6 + - description: power domain of IMX_SC_R_SAI_7 + - description: power domain of IMX_SC_R_SPDIF_0 + - description: power domain of IMX_SC_R_SPDIF_1 + - description: power domain of IMX_SC_R_MQS_0 + + clocks: + minItems: 27 + maxItems: 27 + + clock-names: + items: + - const: aud_rec_clk0_lpcg_clk + - const: aud_rec_clk1_lpcg_clk + - const: aud_pll_div_clk0_lpcg_clk + - const: aud_pll_div_clk1_lpcg_clk + - const: mlb_clk + - const: hdmi_rx_mclk + - const: ext_aud_mclk0 + - const: ext_aud_mclk1 + - const: esai0_rx_clk + - const: esai0_rx_hf_clk + - const: esai0_tx_clk + - const: esai0_tx_hf_clk + - const: esai1_rx_clk + - const: esai1_rx_hf_clk + - const: esai1_tx_clk + - const: esai1_tx_hf_clk + - const: spdif0_rx + - const: spdif1_rx + - const: sai0_rx_bclk + - const: sai0_tx_bclk + - const: sai1_rx_bclk + - const: sai1_tx_bclk + - const: sai2_rx_bclk + - const: sai3_rx_bclk + - const: sai4_rx_bclk + - const: sai5_tx_bclk + - const: sai6_rx_bclk + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8dxl-acm + then: + properties: + power-domains: + items: + - description: power domain of IMX_SC_R_AUDIO_CLK_0 + - description: power domain of IMX_SC_R_AUDIO_CLK_1 + - description: power domain of IMX_SC_R_MCLK_OUT_0 + - description: power domain of IMX_SC_R_MCLK_OUT_1 + - description: power domain of IMX_SC_R_AUDIO_PLL_0 + - description: power domain of IMX_SC_R_AUDIO_PLL_1 + - description: power domain of IMX_SC_R_ASRC_0 + - description: power domain of IMX_SC_R_SAI_0 + - description: power domain of IMX_SC_R_SAI_1 + - description: power domain of IMX_SC_R_SAI_2 + - description: power domain of IMX_SC_R_SAI_3 + - description: power domain of IMX_SC_R_SPDIF_0 + - description: power domain of IMX_SC_R_MQS_0 + + clocks: + minItems: 13 + maxItems: 13 + + clock-names: + items: + - const: aud_rec_clk0_lpcg_clk + - const: aud_rec_clk1_lpcg_clk + - const: aud_pll_div_clk0_lpcg_clk + - const: aud_pll_div_clk1_lpcg_clk + - const: ext_aud_mclk0 + - const: ext_aud_mclk1 + - const: spdif0_rx + - const: sai0_rx_bclk + - const: sai0_tx_bclk + - const: sai1_rx_bclk + - const: sai1_tx_bclk + - const: sai2_rx_bclk + - const: sai3_rx_bclk + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + #include + #include + + clock-controller@59e00000 { + compatible = "fsl,imx8qxp-acm"; + reg = <0x59e00000 0x1d0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&clk_ext_aud_mclk0>, + <&clk_ext_aud_mclk1>, + <&clk_esai0_rx_clk>, + <&clk_esai0_rx_hf_clk>, + <&clk_esai0_tx_clk>, + <&clk_esai0_tx_hf_clk>, + <&clk_spdif0_rx>, + <&clk_sai0_rx_bclk>, + <&clk_sai0_tx_bclk>, + <&clk_sai1_rx_bclk>, + <&clk_sai1_tx_bclk>, + <&clk_sai2_rx_bclk>, + <&clk_sai3_rx_bclk>, + <&clk_sai4_rx_bclk>; + clock-names = "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", + "sai4_rx_bclk"; + }; diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h index 2e60ce4d2622..2242ff54fc5e 100644 --- a/include/dt-bindings/clock/imx8-clock.h +++ b/include/dt-bindings/clock/imx8-clock.h @@ -164,4 +164,32 @@ #define IMX_ADMA_LPCG_CLK_END 45 +#define IMX_ADMA_ACM_AUD_CLK0_SEL 0 +#define IMX_ADMA_ACM_AUD_CLK1_SEL 1 +#define IMX_ADMA_ACM_MCLKOUT0_SEL 2 +#define IMX_ADMA_ACM_MCLKOUT1_SEL 3 +#define IMX_ADMA_ACM_ESAI0_MCLK_SEL 4 +#define IMX_ADMA_ACM_ESAI1_MCLK_SEL 5 +#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 6 +#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 7 +#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 8 +#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 9 +#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 10 +#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 11 +#define IMX_ADMA_ACM_SAI0_MCLK_SEL 12 +#define IMX_ADMA_ACM_SAI1_MCLK_SEL 13 +#define IMX_ADMA_ACM_SAI2_MCLK_SEL 14 +#define IMX_ADMA_ACM_SAI3_MCLK_SEL 15 +#define IMX_ADMA_ACM_SAI4_MCLK_SEL 16 +#define IMX_ADMA_ACM_SAI5_MCLK_SEL 17 +#define IMX_ADMA_ACM_SAI6_MCLK_SEL 18 +#define IMX_ADMA_ACM_SAI7_MCLK_SEL 19 +#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 20 +#define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL 21 +#define IMX_ADMA_ACM_MQS_TX_CLK_SEL 22 +#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 23 +#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 24 + +#define IMX_ADMA_ACM_CLK_END 25 + #endif /* __DT_BINDINGS_CLOCK_IMX_H */ From d3a0946d7ac9ad844a196f0f2af696fde6b0728d Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 25 Jul 2023 12:56:24 +0800 Subject: [PATCH 07/37] clk: imx: imx8: add audio clock mux driver The Audio Clock Mux (ACM) is a collection of control registers and multiplexers that are used to route the audio source clocks to the audio peripherals. Each audio peripheral has its dedicated audio clock mux (which differ based on usage) and control register. Signed-off-by: Shengjiu Wang Reviewed-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/1690260984-25744-3-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/Makefile | 3 +- drivers/clk/imx/clk-imx8-acm.c | 476 +++++++++++++++++++++++++++++++++ 2 files changed, 478 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-imx8-acm.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index ae9d84ef046b..d4b8e10b1970 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -32,11 +32,12 @@ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_CLK_IMX93) += clk-imx93.o -obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o +obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-acm.o clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \ clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o \ clk-imx8dxl-rsrc.o clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o +clk-imx-acm-$(CONFIG_CLK_IMX8QXP) = clk-imx8-acm.o obj-$(CONFIG_CLK_IMX8ULP) += clk-imx8ulp.o diff --git a/drivers/clk/imx/clk-imx8-acm.c b/drivers/clk/imx/clk-imx8-acm.c new file mode 100644 index 000000000000..1e82f72b75c6 --- /dev/null +++ b/drivers/clk/imx/clk-imx8-acm.c @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2023 NXP +// + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +/** + * struct clk_imx_acm_pm_domains - structure for multi power domain + * @pd_dev: power domain device + * @pd_dev_link: power domain device link + * @num_domains: power domain nummber + */ +struct clk_imx_acm_pm_domains { + struct device **pd_dev; + struct device_link **pd_dev_link; + int num_domains; +}; + +/** + * struct clk_imx8_acm_sel - for clock mux + * @name: clock name + * @clkid: clock id + * @parents: clock parents + * @num_parents: clock parents number + * @reg: register offset + * @shift: bit shift in register + * @width: bits width + */ +struct clk_imx8_acm_sel { + const char *name; + int clkid; + const struct clk_parent_data *parents; /* For mux */ + int num_parents; + u32 reg; + u8 shift; + u8 width; +}; + +/** + * struct imx8_acm_soc_data - soc specific data + * @sels: pointer to struct clk_imx8_acm_sel + * @num_sels: numbers of items + */ +struct imx8_acm_soc_data { + struct clk_imx8_acm_sel *sels; + unsigned int num_sels; +}; + +/** + * struct imx8_acm_priv - private structure + * @dev_pm: multi power domain + * @soc_data: pointer to soc data + * @reg: base address of registers + * @regs: save registers for suspend + */ +struct imx8_acm_priv { + struct clk_imx_acm_pm_domains dev_pm; + const struct imx8_acm_soc_data *soc_data; + void __iomem *reg; + u32 regs[IMX_ADMA_ACM_CLK_END]; +}; + +static const struct clk_parent_data imx8qm_aud_clk_sels[] = { + { .fw_name = "aud_rec_clk0_lpcg_clk" }, + { .fw_name = "aud_rec_clk1_lpcg_clk" }, + { .fw_name = "mlb_clk" }, + { .fw_name = "hdmi_rx_mclk" }, + { .fw_name = "ext_aud_mclk0" }, + { .fw_name = "ext_aud_mclk1" }, + { .fw_name = "esai0_rx_clk" }, + { .fw_name = "esai0_rx_hf_clk" }, + { .fw_name = "esai0_tx_clk" }, + { .fw_name = "esai0_tx_hf_clk" }, + { .fw_name = "esai1_rx_clk" }, + { .fw_name = "esai1_rx_hf_clk" }, + { .fw_name = "esai1_tx_clk" }, + { .fw_name = "esai1_tx_hf_clk" }, + { .fw_name = "spdif0_rx" }, + { .fw_name = "spdif1_rx" }, + { .fw_name = "sai0_rx_bclk" }, + { .fw_name = "sai0_tx_bclk" }, + { .fw_name = "sai1_rx_bclk" }, + { .fw_name = "sai1_tx_bclk" }, + { .fw_name = "sai2_rx_bclk" }, + { .fw_name = "sai3_rx_bclk" }, + { .fw_name = "sai4_rx_bclk" }, +}; + +static const struct clk_parent_data imx8qm_mclk_out_sels[] = { + { .fw_name = "aud_rec_clk0_lpcg_clk" }, + { .fw_name = "aud_rec_clk1_lpcg_clk" }, + { .fw_name = "mlb_clk" }, + { .fw_name = "hdmi_rx_mclk" }, + { .fw_name = "spdif0_rx" }, + { .fw_name = "spdif1_rx" }, + { .fw_name = "sai4_rx_bclk" }, + { .fw_name = "sai6_rx_bclk" }, +}; + +static const struct clk_parent_data imx8qm_mclk_sels[] = { + { .fw_name = "aud_pll_div_clk0_lpcg_clk" }, + { .fw_name = "aud_pll_div_clk1_lpcg_clk" }, + { .fw_name = "acm_aud_clk0_sel" }, + { .fw_name = "acm_aud_clk1_sel" }, +}; + +static const struct clk_parent_data imx8qm_asrc_mux_clk_sels[] = { + { .fw_name = "sai4_rx_bclk" }, + { .fw_name = "sai5_tx_bclk" }, + { .index = -1 }, + { .fw_name = "mlb_clk" }, + +}; + +static struct clk_imx8_acm_sel imx8qm_sels[] = { + { "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x000000, 0, 5 }, + { "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x010000, 0, 5 }, + { "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x020000, 0, 3 }, + { "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x030000, 0, 3 }, + { "acm_asrc0_mclk_sel", IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL, imx8qm_asrc_mux_clk_sels, ARRAY_SIZE(imx8qm_asrc_mux_clk_sels), 0x040000, 0, 2 }, + { "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x060000, 0, 2 }, + { "acm_esai1_mclk_sel", IMX_ADMA_ACM_ESAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x070000, 0, 2 }, + { "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0E0000, 0, 2 }, + { "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0F0000, 0, 2 }, + { "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x100000, 0, 2 }, + { "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x110000, 0, 2 }, + { "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x120000, 0, 2 }, + { "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x130000, 0, 2 }, + { "acm_sai6_mclk_sel", IMX_ADMA_ACM_SAI6_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x140000, 0, 2 }, + { "acm_sai7_mclk_sel", IMX_ADMA_ACM_SAI7_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x150000, 0, 2 }, + { "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1A0000, 0, 2 }, + { "acm_spdif1_mclk_sel", IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1B0000, 0, 2 }, + { "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1C0000, 0, 2 }, +}; + +static const struct clk_parent_data imx8qxp_aud_clk_sels[] = { + { .fw_name = "aud_rec_clk0_lpcg_clk" }, + { .fw_name = "aud_rec_clk1_lpcg_clk" }, + { .fw_name = "ext_aud_mclk0" }, + { .fw_name = "ext_aud_mclk1" }, + { .fw_name = "esai0_rx_clk" }, + { .fw_name = "esai0_rx_hf_clk" }, + { .fw_name = "esai0_tx_clk" }, + { .fw_name = "esai0_tx_hf_clk" }, + { .fw_name = "spdif0_rx" }, + { .fw_name = "sai0_rx_bclk" }, + { .fw_name = "sai0_tx_bclk" }, + { .fw_name = "sai1_rx_bclk" }, + { .fw_name = "sai1_tx_bclk" }, + { .fw_name = "sai2_rx_bclk" }, + { .fw_name = "sai3_rx_bclk" }, +}; + +static const struct clk_parent_data imx8qxp_mclk_out_sels[] = { + { .fw_name = "aud_rec_clk0_lpcg_clk" }, + { .fw_name = "aud_rec_clk1_lpcg_clk" }, + { .index = -1 }, + { .index = -1 }, + { .fw_name = "spdif0_rx" }, + { .index = -1 }, + { .index = -1 }, + { .fw_name = "sai4_rx_bclk" }, +}; + +static const struct clk_parent_data imx8qxp_mclk_sels[] = { + { .fw_name = "aud_pll_div_clk0_lpcg_clk" }, + { .fw_name = "aud_pll_div_clk1_lpcg_clk" }, + { .fw_name = "acm_aud_clk0_sel" }, + { .fw_name = "acm_aud_clk1_sel" }, +}; + +static struct clk_imx8_acm_sel imx8qxp_sels[] = { + { "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x000000, 0, 5 }, + { "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x010000, 0, 5 }, + { "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x020000, 0, 3 }, + { "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x030000, 0, 3 }, + { "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x060000, 0, 2 }, + { "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0E0000, 0, 2 }, + { "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0F0000, 0, 2 }, + { "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x100000, 0, 2 }, + { "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x110000, 0, 2 }, + { "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x140000, 0, 2 }, + { "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x150000, 0, 2 }, + { "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1A0000, 0, 2 }, + { "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1C0000, 0, 2 }, +}; + +static const struct clk_parent_data imx8dxl_aud_clk_sels[] = { + { .fw_name = "aud_rec_clk0_lpcg_clk" }, + { .fw_name = "aud_rec_clk1_lpcg_clk" }, + { .fw_name = "ext_aud_mclk0" }, + { .fw_name = "ext_aud_mclk1" }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .fw_name = "spdif0_rx" }, + { .fw_name = "sai0_rx_bclk" }, + { .fw_name = "sai0_tx_bclk" }, + { .fw_name = "sai1_rx_bclk" }, + { .fw_name = "sai1_tx_bclk" }, + { .fw_name = "sai2_rx_bclk" }, + { .fw_name = "sai3_rx_bclk" }, +}; + +static const struct clk_parent_data imx8dxl_mclk_out_sels[] = { + { .fw_name = "aud_rec_clk0_lpcg_clk" }, + { .fw_name = "aud_rec_clk1_lpcg_clk" }, + { .index = -1 }, + { .index = -1 }, + { .fw_name = "spdif0_rx" }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, +}; + +static const struct clk_parent_data imx8dxl_mclk_sels[] = { + { .fw_name = "aud_pll_div_clk0_lpcg_clk" }, + { .fw_name = "aud_pll_div_clk1_lpcg_clk" }, + { .fw_name = "acm_aud_clk0_sel" }, + { .fw_name = "acm_aud_clk1_sel" }, +}; + +static struct clk_imx8_acm_sel imx8dxl_sels[] = { + { "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x000000, 0, 5 }, + { "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x010000, 0, 5 }, + { "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x020000, 0, 3 }, + { "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x030000, 0, 3 }, + { "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0E0000, 0, 2 }, + { "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0F0000, 0, 2 }, + { "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x100000, 0, 2 }, + { "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x110000, 0, 2 }, + { "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1A0000, 0, 2 }, + { "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1C0000, 0, 2 }, +}; + +/** + * clk_imx_acm_attach_pm_domains: attach multi power domains + * @dev: device pointer + * @dev_pm: power domains for device + */ +static int clk_imx_acm_attach_pm_domains(struct device *dev, + struct clk_imx_acm_pm_domains *dev_pm) +{ + int ret; + int i; + + dev_pm->num_domains = of_count_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells"); + if (dev_pm->num_domains <= 1) + return 0; + + dev_pm->pd_dev = devm_kmalloc_array(dev, dev_pm->num_domains, + sizeof(*dev_pm->pd_dev), + GFP_KERNEL); + if (!dev_pm->pd_dev) + return -ENOMEM; + + dev_pm->pd_dev_link = devm_kmalloc_array(dev, + dev_pm->num_domains, + sizeof(*dev_pm->pd_dev_link), + GFP_KERNEL); + if (!dev_pm->pd_dev_link) + return -ENOMEM; + + for (i = 0; i < dev_pm->num_domains; i++) { + dev_pm->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i); + if (IS_ERR(dev_pm->pd_dev[i])) + return PTR_ERR(dev_pm->pd_dev[i]); + + dev_pm->pd_dev_link[i] = device_link_add(dev, + dev_pm->pd_dev[i], + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (IS_ERR(dev_pm->pd_dev_link[i])) { + dev_pm_domain_detach(dev_pm->pd_dev[i], false); + ret = PTR_ERR(dev_pm->pd_dev_link[i]); + goto detach_pm; + } + } + return 0; + +detach_pm: + while (--i >= 0) { + device_link_del(dev_pm->pd_dev_link[i]); + dev_pm_domain_detach(dev_pm->pd_dev[i], false); + } + return ret; +} + +/** + * clk_imx_acm_detach_pm_domains: detach multi power domains + * @dev: deivice pointer + * @dev_pm: multi power domain for device + */ +static int clk_imx_acm_detach_pm_domains(struct device *dev, + struct clk_imx_acm_pm_domains *dev_pm) +{ + int i; + + if (dev_pm->num_domains <= 1) + return 0; + + for (i = 0; i < dev_pm->num_domains; i++) { + device_link_del(dev_pm->pd_dev_link[i]); + dev_pm_domain_detach(dev_pm->pd_dev[i], false); + } + + return 0; +} + +static int imx8_acm_clk_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_hw_data; + struct device *dev = &pdev->dev; + struct clk_imx8_acm_sel *sels; + struct imx8_acm_priv *priv; + struct clk_hw **hws; + void __iomem *base; + int ret; + int i; + + base = devm_of_iomap(dev, dev->of_node, 0, NULL); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->reg = base; + priv->soc_data = of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + clk_hw_data = devm_kzalloc(&pdev->dev, struct_size(clk_hw_data, hws, IMX_ADMA_ACM_CLK_END), + GFP_KERNEL); + if (!clk_hw_data) + return -ENOMEM; + + clk_hw_data->num = IMX_ADMA_ACM_CLK_END; + hws = clk_hw_data->hws; + + ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm); + if (ret) + return ret; + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + sels = priv->soc_data->sels; + for (i = 0; i < priv->soc_data->num_sels; i++) { + hws[sels[i].clkid] = devm_clk_hw_register_mux_parent_data_table(dev, + sels[i].name, sels[i].parents, + sels[i].num_parents, 0, + base + sels[i].reg, + sels[i].shift, sels[i].width, + 0, NULL, NULL); + if (IS_ERR(hws[sels[i].clkid])) { + pm_runtime_disable(&pdev->dev); + goto err_clk_register; + } + } + + imx_check_clk_hws(hws, IMX_ADMA_ACM_CLK_END); + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + dev_err(dev, "failed to register hws for ACM\n"); + pm_runtime_disable(&pdev->dev); + } + +err_clk_register: + + pm_runtime_put_sync(&pdev->dev); + + return ret; +} + +static int imx8_acm_clk_remove(struct platform_device *pdev) +{ + struct imx8_acm_priv *priv = dev_get_drvdata(&pdev->dev); + + pm_runtime_disable(&pdev->dev); + + clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm); + + return 0; +} + +static const struct imx8_acm_soc_data imx8qm_acm_data = { + .sels = imx8qm_sels, + .num_sels = ARRAY_SIZE(imx8qm_sels), +}; + +static const struct imx8_acm_soc_data imx8qxp_acm_data = { + .sels = imx8qxp_sels, + .num_sels = ARRAY_SIZE(imx8qxp_sels), +}; + +static const struct imx8_acm_soc_data imx8dxl_acm_data = { + .sels = imx8dxl_sels, + .num_sels = ARRAY_SIZE(imx8dxl_sels), +}; + +static const struct of_device_id imx8_acm_match[] = { + { .compatible = "fsl,imx8qm-acm", .data = &imx8qm_acm_data }, + { .compatible = "fsl,imx8qxp-acm", .data = &imx8qxp_acm_data }, + { .compatible = "fsl,imx8dxl-acm", .data = &imx8dxl_acm_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8_acm_match); + +static int __maybe_unused imx8_acm_runtime_suspend(struct device *dev) +{ + struct imx8_acm_priv *priv = dev_get_drvdata(dev); + struct clk_imx8_acm_sel *sels; + int i; + + sels = priv->soc_data->sels; + + for (i = 0; i < priv->soc_data->num_sels; i++) + priv->regs[i] = readl_relaxed(priv->reg + sels[i].reg); + + return 0; +} + +static int __maybe_unused imx8_acm_runtime_resume(struct device *dev) +{ + struct imx8_acm_priv *priv = dev_get_drvdata(dev); + struct clk_imx8_acm_sel *sels; + int i; + + sels = priv->soc_data->sels; + + for (i = 0; i < priv->soc_data->num_sels; i++) + writel_relaxed(priv->regs[i], priv->reg + sels[i].reg); + + return 0; +} + +static const struct dev_pm_ops imx8_acm_pm_ops = { + SET_RUNTIME_PM_OPS(imx8_acm_runtime_suspend, + imx8_acm_runtime_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver imx8_acm_clk_driver = { + .driver = { + .name = "imx8-acm", + .of_match_table = imx8_acm_match, + .pm = &imx8_acm_pm_ops, + }, + .probe = imx8_acm_clk_probe, + .remove = imx8_acm_clk_remove, +}; +module_platform_driver(imx8_acm_clk_driver); + +MODULE_AUTHOR("Shengjiu Wang "); +MODULE_DESCRIPTION("Freescale i.MX8 Audio Clock Mux driver"); +MODULE_LICENSE("GPL"); From 3f0cdb945471f1abd1cf4d172190e9c489c5052a Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 25 Jun 2023 20:33:39 +0800 Subject: [PATCH 08/37] clk: imx: pllv4: Fix SPLL2 MULT range The SPLL2 on iMX8ULP is different with other frac PLLs, it can support VCO from 650Mhz to 1Ghz. According to RM, the MULT is using a range from 27 to 54, not some fixed values. If using current PLL implementation, some clock rate can't be supported. Fix the issue by adding new type for the SPLL2 and use MULT range to replace MULT table Fixes: 5f0601c47c33 ("clk: imx: Update the pllv4 to support imx8ulp") Reviewed-by: Peng Fan Reviewed-by: Jacky Bai Signed-off-by: Ye Li Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20230625123340.4067536-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pllv4.c | 44 +++++++++++++++++++++++++++++-------- drivers/clk/imx/clk.h | 1 + 2 files changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c index 6e7e34571fc8..9b136c951762 100644 --- a/drivers/clk/imx/clk-pllv4.c +++ b/drivers/clk/imx/clk-pllv4.c @@ -44,11 +44,15 @@ struct clk_pllv4 { u32 cfg_offset; u32 num_offset; u32 denom_offset; + bool use_mult_range; }; /* Valid PLL MULT Table */ static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16}; +/* Valid PLL MULT range, (max, min) */ +static const int pllv4_mult_range[] = {54, 27}; + #define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw) #define LOCK_TIMEOUT_US USEC_PER_MSEC @@ -94,17 +98,30 @@ static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw, static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { + struct clk_pllv4 *pll = to_clk_pllv4(hw); unsigned long parent_rate = *prate; unsigned long round_rate, i; u32 mfn, mfd = DEFAULT_MFD; bool found = false; u64 temp64; + u32 mult; - for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) { - round_rate = parent_rate * pllv4_mult_table[i]; - if (rate >= round_rate) { + if (pll->use_mult_range) { + temp64 = (u64)rate; + do_div(temp64, parent_rate); + mult = temp64; + if (mult >= pllv4_mult_range[1] && + mult <= pllv4_mult_range[0]) { + round_rate = parent_rate * mult; found = true; - break; + } + } else { + for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) { + round_rate = parent_rate * pllv4_mult_table[i]; + if (rate >= round_rate) { + found = true; + break; + } } } @@ -138,14 +155,20 @@ static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate, return round_rate + (u32)temp64; } -static bool clk_pllv4_is_valid_mult(unsigned int mult) +static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int mult) { int i; /* check if mult is in valid MULT table */ - for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) { - if (pllv4_mult_table[i] == mult) + if (pll->use_mult_range) { + if (mult >= pllv4_mult_range[1] && + mult <= pllv4_mult_range[0]) return true; + } else { + for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) { + if (pllv4_mult_table[i] == mult) + return true; + } } return false; @@ -160,7 +183,7 @@ static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate, mult = rate / parent_rate; - if (!clk_pllv4_is_valid_mult(mult)) + if (!clk_pllv4_is_valid_mult(pll, mult)) return -EINVAL; if (parent_rate <= MAX_MFD) @@ -227,10 +250,13 @@ struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name, pll->base = base; - if (type == IMX_PLLV4_IMX8ULP) { + if (type == IMX_PLLV4_IMX8ULP || + type == IMX_PLLV4_IMX8ULP_1GHZ) { pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET; pll->num_offset = IMX8ULP_PLL_NUM_OFFSET; pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET; + if (type == IMX_PLLV4_IMX8ULP_1GHZ) + pll->use_mult_range = true; } else { pll->cfg_offset = PLL_CFG_OFFSET; pll->num_offset = PLL_NUM_OFFSET; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index af19d9f6aed0..adb7ad649a0d 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -45,6 +45,7 @@ enum imx_pll14xx_type { enum imx_pllv4_type { IMX_PLLV4_IMX7ULP, IMX_PLLV4_IMX8ULP, + IMX_PLLV4_IMX8ULP_1GHZ, }; enum imx_pfdv2_type { From 7653a59be8af043adc4c09473975a860e6055ff9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 25 Jun 2023 20:33:40 +0800 Subject: [PATCH 09/37] clk: imx: imx8ulp: update SPLL2 type The SPLL2 on iMX8ULP is different with other frac PLLs, it can support VCO from 650Mhz to 1Ghz. Following the changes to pllv4, use the new type IMX_PLLV4_IMX8ULP_1GHZ. Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp") Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20230625123340.4067536-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8ulp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8ulp.c b/drivers/clk/imx/clk-imx8ulp.c index e308c88cb801..1b04e2fc78ad 100644 --- a/drivers/clk/imx/clk-imx8ulp.c +++ b/drivers/clk/imx/clk-imx8ulp.c @@ -167,7 +167,7 @@ static int imx8ulp_clk_cgc1_init(struct platform_device *pdev) clks[IMX8ULP_CLK_SPLL2_PRE_SEL] = imx_clk_hw_mux_flags("spll2_pre_sel", base + 0x510, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); clks[IMX8ULP_CLK_SPLL3_PRE_SEL] = imx_clk_hw_mux_flags("spll3_pre_sel", base + 0x610, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); - clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll2", "spll2_pre_sel", base + 0x500); + clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP_1GHZ, "spll2", "spll2_pre_sel", base + 0x500); clks[IMX8ULP_CLK_SPLL3] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll3", "spll3_pre_sel", base + 0x600); clks[IMX8ULP_CLK_SPLL3_VCODIV] = imx_clk_hw_divider("spll3_vcodiv", "spll3", base + 0x604, 0, 6); From c30f600f1f41dcf5ef0fb02e9a201f9b2e8f31bd Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Mon, 31 Jul 2023 16:21:49 +0200 Subject: [PATCH 10/37] clk: imx8mp: fix sai4 clock The reference manual don't mention a SAI4 hardware block. This would be clock slice 78 which is skipped (TRM, page 237). Remove any reference to this clock to align the driver with the reality. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Acked-by: Stephen Boyd Signed-off-by: Marco Felsch Link: https://lore.kernel.org/r/20230731142150.3186650-1-m.felsch@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8mp.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 1469249386dd..670aa2bab301 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -178,10 +178,6 @@ static const char * const imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "au "video_pll1_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; -static const char * const imx8mp_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", - "clk_ext1", "clk_ext2", }; - static const char * const imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; @@ -567,7 +563,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels, ccm_base + 0xa580); hws[IMX8MP_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels, ccm_base + 0xa600); hws[IMX8MP_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels, ccm_base + 0xa680); - hws[IMX8MP_CLK_SAI4] = imx8m_clk_hw_composite("sai4", imx8mp_sai4_sels, ccm_base + 0xa700); hws[IMX8MP_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels, ccm_base + 0xa780); hws[IMX8MP_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels, ccm_base + 0xa800); hws[IMX8MP_CLK_ENET_QOS] = imx8m_clk_hw_composite("enet_qos", imx8mp_enet_qos_sels, ccm_base + 0xa880); From 35ec2abb54726e1a72c570f6465811e049d81cbc Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Mon, 31 Jul 2023 16:21:50 +0200 Subject: [PATCH 11/37] dt-bindings: clocks: imx8mp: make sai4 a dummy clock The hardware don't have a SAI4 instance so remove the define. Use a comment to keep it as reference and to avoid confusion. Fixes: 108869144739 ("dt-bindings: imx: Add clock binding doc for i.MX8MP") Acked-by: Stephen Boyd Acked-by: Rob Herring Signed-off-by: Marco Felsch Link: https://lore.kernel.org/r/20230731142150.3186650-2-m.felsch@pengutronix.de Signed-off-by: Abel Vesa --- include/dt-bindings/clock/imx8mp-clock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 3f28ce685f41..11cb0a4fe999 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -130,7 +130,7 @@ #define IMX8MP_CLK_SAI1 123 #define IMX8MP_CLK_SAI2 124 #define IMX8MP_CLK_SAI3 125 -#define IMX8MP_CLK_SAI4 126 +/* #define IMX8MP_CLK_SAI4 126 */ #define IMX8MP_CLK_SAI5 127 #define IMX8MP_CLK_SAI6 128 #define IMX8MP_CLK_ENET_QOS 129 From b8a06b125c245eb946d88847e052294a85b206c3 Mon Sep 17 00:00:00 2001 From: Martin Kaiser Date: Wed, 2 Aug 2023 20:40:45 +0200 Subject: [PATCH 12/37] clk: imx25: print silicon revision during init Print the imx25 silicon revision when the clocks are initialised. Use the same mechanism as for imx27, i.e. call mx25_revision. This function is unused at the moment. Signed-off-by: Martin Kaiser Reviewed-by: Fabio Estevam Acked-by: Arnd Bergmann Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20230802184046.153394-2-martin@kaiser.cx Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx25.c | 3 +++ include/soc/imx/revision.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c index cc013b343e62..bee3da2e21e1 100644 --- a/drivers/clk/imx/clk-imx25.c +++ b/drivers/clk/imx/clk-imx25.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "clk.h" @@ -220,6 +221,8 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base) imx_register_uart_clocks(); + imx_print_silicon_rev("i.MX25", mx25_revision()); + return 0; } diff --git a/include/soc/imx/revision.h b/include/soc/imx/revision.h index b2a55dafaf0a..b122d2fc8881 100644 --- a/include/soc/imx/revision.h +++ b/include/soc/imx/revision.h @@ -22,6 +22,7 @@ #define IMX_CHIP_REVISION_3_3 0x33 #define IMX_CHIP_REVISION_UNKNOWN 0xff +int mx25_revision(void); int mx27_revision(void); int mx31_revision(void); int mx35_revision(void); From 5dc176079b7a8ba7ff89db10e0c9784856c79d7f Mon Sep 17 00:00:00 2001 From: Martin Kaiser Date: Wed, 2 Aug 2023 20:40:46 +0200 Subject: [PATCH 13/37] clk: imx25: make __mx25_clocks_init return void The __mx25_clocks_init function always returns 0 and its only caller does not check the return value. Let's remove it. Signed-off-by: Martin Kaiser Reviewed-by: Fabio Estevam Acked-by: Arnd Bergmann Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20230802184046.153394-3-martin@kaiser.cx Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx25.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c index bee3da2e21e1..c566be848c2d 100644 --- a/drivers/clk/imx/clk-imx25.c +++ b/drivers/clk/imx/clk-imx25.c @@ -74,7 +74,7 @@ enum mx25_clks { static struct clk *clk[clk_max]; -static int __init __mx25_clocks_init(void __iomem *ccm_base) +static void __init __mx25_clocks_init(void __iomem *ccm_base) { BUG_ON(!ccm_base); @@ -222,8 +222,6 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base) imx_register_uart_clocks(); imx_print_silicon_rev("i.MX25", mx25_revision()); - - return 0; } static void __init mx25_clocks_init_dt(struct device_node *np) From 4dd432d985ef258e3bc436e568fba4b987b59171 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 7 Aug 2023 10:22:00 +0200 Subject: [PATCH 14/37] clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op Reconfiguring the clock divider to the exact same value is observed on an i.MX8MN to often cause a longer than usual clock pause, probably because the divider restarts counting whenever the register is rewritten. This issue doesn't show up normally, because the clock framework will take care to not call set_rate when the clock rate is the same. However, when we reconfigure an upstream clock, the common code will call set_rate with the newly calculated rate on all children, e.g.: - sai5 is running normally and divides Audio PLL out by 16. - Audio PLL rate is increased by 32Hz (glitch-free kdiv change) - rates for children are recalculated and rates are set recursively - imx8m_clk_composite_divider_set_rate(sai5) is called with 32/16 = 2Hz more - imx8m_clk_composite_divider_set_rate computes same divider as before - divider register is written, so it restarts counting from zero and MCLK is briefly paused, so instead of e.g. 40ns, MCLK is low for 120ns. Some external clock consumers can be upset by such unexpected clock pauses, so let's make sure we only rewrite the divider value when the value to be written is actually different. Fixes: d3ff9728134e ("clk: imx: Add imx composite clock") Signed-off-by: Ahmad Fatoum Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/20230807082201.2332746-1-a.fatoum@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-composite-8m.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 7a6e3ce97133..27a08c50ac1d 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -97,7 +97,7 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, int prediv_value; int div_value; int ret; - u32 val; + u32 orig, val; ret = imx8m_clk_composite_compute_dividers(rate, parent_rate, &prediv_value, &div_value); @@ -106,13 +106,15 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, spin_lock_irqsave(divider->lock, flags); - val = readl(divider->reg); - val &= ~((clk_div_mask(divider->width) << divider->shift) | - (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); + orig = readl(divider->reg); + val = orig & ~((clk_div_mask(divider->width) << divider->shift) | + (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); val |= (u32)(prediv_value - 1) << divider->shift; val |= (u32)(div_value - 1) << PCG_DIV_SHIFT; - writel(val, divider->reg); + + if (val != orig) + writel(val, divider->reg); spin_unlock_irqrestore(divider->lock, flags); From 37cfd5e457cbdcd030f378127ff2d62776f641e7 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Mon, 7 Aug 2023 10:47:43 +0200 Subject: [PATCH 15/37] clk: imx: pll14xx: align pdiv with reference manual The PLL14xx hardware can be found on i.MX8M{M,N,P} SoCs and always come with a 6-bit pre-divider. Neither the reference manuals nor the datasheets of these SoCs do mention any restrictions. Furthermore the current code doesn't respect the restrictions from the comment too. Therefore drop the restriction and align the max pre-divider (pdiv) value to 63 to get more accurate frequencies. Fixes: b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") Cc: stable@vger.kernel.org Signed-off-by: Marco Felsch Reviewed-by: Abel Vesa Reviewed-by: Adam Ford Signed-off-by: Philipp Zabel Acked-by: Sascha Hauer Tested-by: Ahmad Fatoum Link: https://lore.kernel.org/r/20230807084744.1184791-1-m.felsch@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 7150c59bbfc9..dc6bc21dff41 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -139,11 +139,10 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat /* * Fractional PLL constrains: * - * a) 6MHz <= prate <= 25MHz - * b) 1 <= p <= 63 (1 <= p <= 4 prate = 24MHz) - * c) 64 <= m <= 1023 - * d) 0 <= s <= 6 - * e) -32768 <= k <= 32767 + * a) 1 <= p <= 63 + * b) 64 <= m <= 1023 + * c) 0 <= s <= 6 + * d) -32768 <= k <= 32767 * * fvco = (m * 65536 + k) * prate / (p * 65536) */ @@ -186,7 +185,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat } /* Finally calculate best values */ - for (pdiv = 1; pdiv <= 7; pdiv++) { + for (pdiv = 1; pdiv <= 63; pdiv++) { for (sdiv = 0; sdiv <= 6; sdiv++) { /* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */ mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate); From 72d00e560d10665e6139c9431956a87ded6e9880 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 7 Aug 2023 10:47:44 +0200 Subject: [PATCH 16/37] clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates"), the driver has the ability to dynamically compute PLL parameters to approximate the requested rates. This is not always used, because the logic is as follows: - Check if the target rate is hardcoded in the frequency table - Check if varying only kdiv is possible, so switch over is glitch free - Compute rate dynamically by iterating over pdiv range If we skip the frequency table for the 1443x PLL, we find that the computed values differ to the hardcoded ones. This can be valid if the hardcoded values guarantee for example an earlier lock-in or if the divisors are chosen, so that other important rates are more likely to be reached glitch-free. For rates (393216000 and 361267200, this doesn't seem to be the case: They are only approximated by existing parameters (393215995 and 361267196 Hz, respectively) and they aren't reachable glitch-free from other hardcoded frequencies. Dropping them from the table allows us to lock-in to these frequencies exactly. This is immediately noticeable because they are the assigned-clock-rates for IMX8MN_AUDIO_PLL1 and IMX8MN_AUDIO_PLL2, respectively and a look into clk_summary so far showed that they were a few Hz short of the target: imx8mn-board:~# grep audio_pll[12]_out /sys/kernel/debug/clk/clk_summary audio_pll2_out 0 0 0 361267196 0 0 50000 N audio_pll1_out 1 1 0 393215995 0 0 50000 Y and afterwards: imx8mn-board:~# grep audio_pll[12]_out /sys/kernel/debug/clk/clk_summary audio_pll2_out 0 0 0 361267200 0 0 50000 N audio_pll1_out 1 1 0 393216000 0 0 50000 Y This change is equivalent to adding following hardcoded values: /* rate mdiv pdiv sdiv kdiv */ PLL_1443X_RATE(393216000, 655, 5, 3, 23593), PLL_1443X_RATE(361267200, 497, 33, 0, -16882), Fixes: 053a4ffe2988 ("clk: imx: imx8mm: fix audio pll setting") Cc: stable@vger.kernel.org # v5.18+ Signed-off-by: Ahmad Fatoum Signed-off-by: Marco Felsch Link: https://lore.kernel.org/r/20230807084744.1184791-2-m.felsch@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index dc6bc21dff41..0d58d85c375e 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -64,8 +64,6 @@ static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(594000000U, 198, 2, 2, 0), PLL_1443X_RATE(519750000U, 173, 2, 2, 16384), - PLL_1443X_RATE(393216000U, 262, 2, 3, 9437), - PLL_1443X_RATE(361267200U, 361, 3, 3, 17511), }; struct imx_pll14xx_clk imx_1443x_pll = { From ec01691c9c631ae465ff0438172738d68bca828b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:28 +0200 Subject: [PATCH 17/37] clk: samsung: exynos3250: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos3250.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 6cc65ccf867c..a02461667664 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -100,6 +100,11 @@ #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_MAIN (CLK_SCLK_MMC2 + 1) +#define CLKS_NR_DMC (CLK_DIV_DMCD + 1) +#define CLKS_NR_ISP (CLK_SCLK_MPWM_ISP + 1) + static const unsigned long exynos3250_cmu_clk_regs[] __initconst = { SRC_LEFTBUS, DIV_LEFTBUS, @@ -807,7 +812,7 @@ static const struct samsung_cmu_info cmu_info __initconst = { .nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks), .cpu_clks = exynos3250_cpu_clks, .nr_cpu_clks = ARRAY_SIZE(exynos3250_cpu_clks), - .nr_clk_ids = CLK_NR_CLKS, + .nr_clk_ids = CLKS_NR_MAIN, .clk_regs = exynos3250_cmu_clk_regs, .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs), }; @@ -923,7 +928,7 @@ static const struct samsung_cmu_info dmc_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(dmc_mux_clks), .div_clks = dmc_div_clks, .nr_div_clks = ARRAY_SIZE(dmc_div_clks), - .nr_clk_ids = NR_CLKS_DMC, + .nr_clk_ids = CLKS_NR_DMC, .clk_regs = exynos3250_cmu_dmc_clk_regs, .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs), }; @@ -1067,7 +1072,7 @@ static const struct samsung_cmu_info isp_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(isp_div_clks), .gate_clks = isp_gate_clks, .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), - .nr_clk_ids = NR_CLKS_ISP, + .nr_clk_ids = CLKS_NR_ISP, }; static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev) From 826951d90658199a1a1098e823b6205aaea09b0f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:29 +0200 Subject: [PATCH 18/37] clk: samsung: exynos4: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos4.c | 5 ++++- drivers/clk/samsung/clk-exynos4412-isp.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 43207257a9cc..4ec41221e68f 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -135,6 +135,9 @@ #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR (CLK_DIV_CORE2 + 1) + /* the exynos4 soc type */ enum exynos4_soc { EXYNOS4210, @@ -1275,7 +1278,7 @@ static void __init exynos4_clk_init(struct device_node *np, if (!reg_base) panic("%s: failed to map registers\n", __func__); - ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS); + ctx = samsung_clk_init(NULL, reg_base, CLKS_NR); hws = ctx->clk_data.hws; samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks, diff --git a/drivers/clk/samsung/clk-exynos4412-isp.c b/drivers/clk/samsung/clk-exynos4412-isp.c index 1470c15e95da..a70c2b06a61a 100644 --- a/drivers/clk/samsung/clk-exynos4412-isp.c +++ b/drivers/clk/samsung/clk-exynos4412-isp.c @@ -22,6 +22,9 @@ #define E4X12_GATE_ISP0 0x0800 #define E4X12_GATE_ISP1 0x0804 +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_ISP (CLK_ISP_DIV_MCUISP1 + 1) + /* * Support for CMU save/restore across system suspends */ @@ -121,7 +124,7 @@ static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev) if (!exynos4x12_save_isp) return -ENOMEM; - ctx = samsung_clk_init(dev, reg_base, CLK_NR_ISP_CLKS); + ctx = samsung_clk_init(dev, reg_base, CLKS_NR_ISP); platform_set_drvdata(pdev, ctx); From 835dc5ac296073b9ca3a2fda86568bb1b9377dee Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:30 +0200 Subject: [PATCH 19/37] clk: samsung: exynos5250: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos5250.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 92fb09922f28..8ebe6155d8b7 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -100,6 +100,9 @@ #define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) #define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR (CLK_MOUT_VPLLSRC + 1) + /* list of PLLs to be registered */ enum exynos5250_plls { apll, mpll, cpll, epll, vpll, gpll, bpll, @@ -797,7 +800,7 @@ static void __init exynos5250_clk_init(struct device_node *np) panic("%s: unable to determine soc\n", __func__); } - ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS); + ctx = samsung_clk_init(NULL, reg_base, CLKS_NR); hws = ctx->clk_data.hws; samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks, From 727d0f0640755eb6e41725d63a506d510078fa8f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:31 +0200 Subject: [PATCH 20/37] clk: samsung: exynos5260: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-5-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos5260.c | 41 +++++++++++++++++++--------- 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c index e05d7323669a..16da6ef5ca0c 100644 --- a/drivers/clk/samsung/clk-exynos5260.c +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -15,6 +15,21 @@ #include +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (PHYCLK_USBDRD30_UDRD30_PHYCLOCK + 1) +#define CLKS_NR_EGL (EGL_DOUT_EGL1 + 1) +#define CLKS_NR_KFC (KFC_DOUT_KFC1 + 1) +#define CLKS_NR_MIF (MIF_SCLK_LPDDR3PHY_WRAP_U0 + 1) +#define CLKS_NR_G3D (G3D_CLK_G3D + 1) +#define CLKS_NR_AUD (AUD_SCLK_I2S + 1) +#define CLKS_NR_MFC (MFC_CLK_SMMU2_MFCM0 + 1) +#define CLKS_NR_GSCL (GSCL_SCLK_CSIS0_WRAP + 1) +#define CLKS_NR_FSYS (FSYS_PHYCLK_USBHOST20 + 1) +#define CLKS_NR_PERI (PERI_SCLK_PCM1 + 1) +#define CLKS_NR_DISP (DISP_MOUT_HDMI_PHY_PIXEL_USER + 1) +#define CLKS_NR_G2D (G2D_CLK_SMMU3_G2D + 1) +#define CLKS_NR_ISP (ISP_SCLK_UART_EXT + 1) + /* * Applicable for all 2550 Type PLLS for Exynos5260, listed below * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL. @@ -135,7 +150,7 @@ static const struct samsung_cmu_info aud_cmu __initconst = { .nr_div_clks = ARRAY_SIZE(aud_div_clks), .gate_clks = aud_gate_clks, .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), - .nr_clk_ids = AUD_NR_CLK, + .nr_clk_ids = CLKS_NR_AUD, .clk_regs = aud_clk_regs, .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), }; @@ -325,7 +340,7 @@ static const struct samsung_cmu_info disp_cmu __initconst = { .nr_div_clks = ARRAY_SIZE(disp_div_clks), .gate_clks = disp_gate_clks, .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), - .nr_clk_ids = DISP_NR_CLK, + .nr_clk_ids = CLKS_NR_DISP, .clk_regs = disp_clk_regs, .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), }; @@ -389,7 +404,7 @@ static const struct samsung_cmu_info egl_cmu __initconst = { .nr_mux_clks = ARRAY_SIZE(egl_mux_clks), .div_clks = egl_div_clks, .nr_div_clks = ARRAY_SIZE(egl_div_clks), - .nr_clk_ids = EGL_NR_CLK, + .nr_clk_ids = CLKS_NR_EGL, .clk_regs = egl_clk_regs, .nr_clk_regs = ARRAY_SIZE(egl_clk_regs), }; @@ -489,7 +504,7 @@ static const struct samsung_cmu_info fsys_cmu __initconst = { .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), .gate_clks = fsys_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), - .nr_clk_ids = FSYS_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS, .clk_regs = fsys_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), }; @@ -580,7 +595,7 @@ static const struct samsung_cmu_info g2d_cmu __initconst = { .nr_div_clks = ARRAY_SIZE(g2d_div_clks), .gate_clks = g2d_gate_clks, .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), - .nr_clk_ids = G2D_NR_CLK, + .nr_clk_ids = CLKS_NR_G2D, .clk_regs = g2d_clk_regs, .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), }; @@ -643,7 +658,7 @@ static const struct samsung_cmu_info g3d_cmu __initconst = { .nr_div_clks = ARRAY_SIZE(g3d_div_clks), .gate_clks = g3d_gate_clks, .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), - .nr_clk_ids = G3D_NR_CLK, + .nr_clk_ids = CLKS_NR_G3D, .clk_regs = g3d_clk_regs, .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), }; @@ -776,7 +791,7 @@ static const struct samsung_cmu_info gscl_cmu __initconst = { .nr_div_clks = ARRAY_SIZE(gscl_div_clks), .gate_clks = gscl_gate_clks, .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), - .nr_clk_ids = GSCL_NR_CLK, + .nr_clk_ids = CLKS_NR_GSCL, .clk_regs = gscl_clk_regs, .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), }; @@ -895,7 +910,7 @@ static const struct samsung_cmu_info isp_cmu __initconst = { .nr_div_clks = ARRAY_SIZE(isp_div_clks), .gate_clks = isp_gate_clks, .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), - .nr_clk_ids = ISP_NR_CLK, + .nr_clk_ids = CLKS_NR_ISP, .clk_regs = isp_clk_regs, .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), }; @@ -959,7 +974,7 @@ static const struct samsung_cmu_info kfc_cmu __initconst = { .nr_mux_clks = ARRAY_SIZE(kfc_mux_clks), .div_clks = kfc_div_clks, .nr_div_clks = ARRAY_SIZE(kfc_div_clks), - .nr_clk_ids = KFC_NR_CLK, + .nr_clk_ids = CLKS_NR_KFC, .clk_regs = kfc_clk_regs, .nr_clk_regs = ARRAY_SIZE(kfc_clk_regs), }; @@ -1015,7 +1030,7 @@ static const struct samsung_cmu_info mfc_cmu __initconst = { .nr_div_clks = ARRAY_SIZE(mfc_div_clks), .gate_clks = mfc_gate_clks, .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), - .nr_clk_ids = MFC_NR_CLK, + .nr_clk_ids = CLKS_NR_MFC, .clk_regs = mfc_clk_regs, .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), }; @@ -1164,7 +1179,7 @@ static const struct samsung_cmu_info mif_cmu __initconst = { .nr_div_clks = ARRAY_SIZE(mif_div_clks), .gate_clks = mif_gate_clks, .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), - .nr_clk_ids = MIF_NR_CLK, + .nr_clk_ids = CLKS_NR_MIF, .clk_regs = mif_clk_regs, .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), }; @@ -1370,7 +1385,7 @@ static const struct samsung_cmu_info peri_cmu __initconst = { .nr_div_clks = ARRAY_SIZE(peri_div_clks), .gate_clks = peri_gate_clks, .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), - .nr_clk_ids = PERI_NR_CLK, + .nr_clk_ids = CLKS_NR_PERI, .clk_regs = peri_clk_regs, .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), }; @@ -1826,7 +1841,7 @@ static const struct samsung_cmu_info top_cmu __initconst = { .nr_gate_clks = ARRAY_SIZE(top_gate_clks), .fixed_clks = fixed_rate_clks, .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks), - .nr_clk_ids = TOP_NR_CLK, + .nr_clk_ids = CLKS_NR_TOP, .clk_regs = top_clk_regs, .nr_clk_regs = ARRAY_SIZE(top_clk_regs), }; From 678417694b8ec22d31d7605352196ffce9bfe128 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:32 +0200 Subject: [PATCH 21/37] clk: samsung: exynos5410: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-6-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos5410.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index d67d67a519a4..2654077211e7 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -56,6 +56,9 @@ #define SRC_KFC 0x28200 #define DIV_KFC0 0x28500 +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR 512 + /* list of PLLs */ enum exynos5410_plls { apll, cpll, epll, mpll, @@ -260,7 +263,7 @@ static const struct samsung_cmu_info cmu __initconst = { .nr_div_clks = ARRAY_SIZE(exynos5410_div_clks), .gate_clks = exynos5410_gate_clks, .nr_gate_clks = ARRAY_SIZE(exynos5410_gate_clks), - .nr_clk_ids = CLK_NR_CLKS, + .nr_clk_ids = CLKS_NR, }; /* register exynos5410 clocks */ From 62eef444cf300ea8a5498a98bfcfd6eb0e53dd3e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:33 +0200 Subject: [PATCH 22/37] clk: samsung: exynos5420: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-7-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos5420.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 1e0cbf762408..199843f12ae5 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -139,6 +139,9 @@ #define SRC_KFC 0x28200 #define DIV_KFC0 0x28500 +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR (CLK_DOUT_PCLK_DREX1 + 1) + /* Exynos5x SoC type */ enum exynos5x_soc { EXYNOS5420, @@ -1587,7 +1590,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_soc = soc; - ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS); + ctx = samsung_clk_init(NULL, reg_base, CLKS_NR); hws = ctx->clk_data.hws; samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, From 6a44298ddbdde13bc7d84168bd4d256521aef439 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:34 +0200 Subject: [PATCH 23/37] clk: samsung: exynos5433: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-8-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos5433.c | 65 +++++++++++++++++++--------- 1 file changed, 44 insertions(+), 21 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index ed43233649ae..6bfc5d0cd924 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -21,6 +21,29 @@ #include "clk-exynos-arm64.h" #include "clk-pll.h" +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (CLK_SCLK_HDMI_SPDIF_DISP + 1) +#define CLKS_NR_CPIF (CLK_SCLK_UFS_MPHY + 1) +#define CLKS_NR_MIF (CLK_SCLK_BUS_PLL_ATLAS + 1) +#define CLKS_NR_PERIC (CLK_DIV_SCLK_SC_IN + 1) +#define CLKS_NR_PERIS (CLK_SCLK_OTP_CON + 1) +#define CLKS_NR_FSYS (CLK_PCIE + 1) +#define CLKS_NR_G2D (CLK_PCLK_SMMU_G2D + 1) +#define CLKS_NR_DISP (CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1) +#define CLKS_NR_AUD (CLK_SCLK_AUD_I2S + 1) +#define CLKS_NR_BUSX (CLK_ACLK_BUS2RTND_400 + 1) +#define CLKS_NR_G3D (CLK_SCLK_HPM_G3D + 1) +#define CLKS_NR_GSCL (CLK_PCLK_SMMU_GSCL2 + 1) +#define CLKS_NR_APOLLO (CLK_SCLK_APOLLO + 1) +#define CLKS_NR_ATLAS (CLK_SCLK_ATLAS + 1) +#define CLKS_NR_MSCL (CLK_SCLK_JPEG + 1) +#define CLKS_NR_MFC (CLK_PCLK_SMMU_MFC_0 + 1) +#define CLKS_NR_HEVC (CLK_PCLK_SMMU_HEVC_0 + 1) +#define CLKS_NR_ISP (CLK_SCLK_PIXELASYNCM_ISPC + 1) +#define CLKS_NR_CAM0 (CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1) +#define CLKS_NR_CAM1 (CLK_SCLK_ISP_CA5 + 1) +#define CLKS_NR_IMEM (CLK_PCLK_SLIMSSS + 1) + /* * Register offset definitions for CMU_TOP */ @@ -798,7 +821,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), .fixed_factor_clks = top_fixed_factor_clks, .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), - .nr_clk_ids = TOP_NR_CLK, + .nr_clk_ids = CLKS_NR_TOP, .clk_regs = top_clk_regs, .nr_clk_regs = ARRAY_SIZE(top_clk_regs), .suspend_regs = top_suspend_regs, @@ -877,7 +900,7 @@ static const struct samsung_cmu_info cpif_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(cpif_div_clks), .gate_clks = cpif_gate_clks, .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks), - .nr_clk_ids = CPIF_NR_CLK, + .nr_clk_ids = CLKS_NR_CPIF, .clk_regs = cpif_clk_regs, .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), .suspend_regs = cpif_suspend_regs, @@ -1531,7 +1554,7 @@ static const struct samsung_cmu_info mif_cmu_info __initconst = { .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), .fixed_factor_clks = mif_fixed_factor_clks, .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), - .nr_clk_ids = MIF_NR_CLK, + .nr_clk_ids = CLKS_NR_MIF, .clk_regs = mif_clk_regs, .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), }; @@ -1730,7 +1753,7 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(peric_div_clks), .gate_clks = peric_gate_clks, .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), - .nr_clk_ids = PERIC_NR_CLK, + .nr_clk_ids = CLKS_NR_PERIC, .clk_regs = peric_clk_regs, .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), .suspend_regs = peric_suspend_regs, @@ -1924,7 +1947,7 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = { static const struct samsung_cmu_info peris_cmu_info __initconst = { .gate_clks = peris_gate_clks, .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), - .nr_clk_ids = PERIS_NR_CLK, + .nr_clk_ids = CLKS_NR_PERIS, .clk_regs = peris_clk_regs, .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), }; @@ -2336,7 +2359,7 @@ static const struct samsung_cmu_info fsys_cmu_info __initconst = { .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), .fixed_clks = fsys_fixed_clks, .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks), - .nr_clk_ids = FSYS_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS, .clk_regs = fsys_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), .suspend_regs = fsys_suspend_regs, @@ -2459,7 +2482,7 @@ static const struct samsung_cmu_info g2d_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(g2d_div_clks), .gate_clks = g2d_gate_clks, .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), - .nr_clk_ids = G2D_NR_CLK, + .nr_clk_ids = CLKS_NR_G2D, .clk_regs = g2d_clk_regs, .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), .suspend_regs = g2d_suspend_regs, @@ -2887,7 +2910,7 @@ static const struct samsung_cmu_info disp_cmu_info __initconst = { .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks), .fixed_factor_clks = disp_fixed_factor_clks, .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks), - .nr_clk_ids = DISP_NR_CLK, + .nr_clk_ids = CLKS_NR_DISP, .clk_regs = disp_clk_regs, .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), .suspend_regs = disp_suspend_regs, @@ -3057,7 +3080,7 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = { .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), .fixed_clks = aud_fixed_clks, .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), - .nr_clk_ids = AUD_NR_CLK, + .nr_clk_ids = CLKS_NR_AUD, .clk_regs = aud_clk_regs, .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), .suspend_regs = aud_suspend_regs, @@ -3189,7 +3212,7 @@ static const struct samsung_gate_clock bus2_gate_clks[] __initconst = { .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \ .gate_clks = bus##id##_gate_clks, \ .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ - .nr_clk_ids = BUSx_NR_CLK + .nr_clk_ids = CLKS_NR_BUSX static const struct samsung_cmu_info bus0_cmu_info __initconst = { CMU_BUS_INFO_CLKS(0), @@ -3340,7 +3363,7 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(g3d_div_clks), .gate_clks = g3d_gate_clks, .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), - .nr_clk_ids = G3D_NR_CLK, + .nr_clk_ids = CLKS_NR_G3D, .clk_regs = g3d_clk_regs, .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), .suspend_regs = g3d_suspend_regs, @@ -3483,7 +3506,7 @@ static const struct samsung_cmu_info gscl_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), .gate_clks = gscl_gate_clks, .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), - .nr_clk_ids = GSCL_NR_CLK, + .nr_clk_ids = CLKS_NR_GSCL, .clk_regs = gscl_clk_regs, .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), .suspend_regs = gscl_suspend_regs, @@ -3693,7 +3716,7 @@ static const struct samsung_cmu_info apollo_cmu_info __initconst = { .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks), .cpu_clks = apollo_cpu_clks, .nr_cpu_clks = ARRAY_SIZE(apollo_cpu_clks), - .nr_clk_ids = APOLLO_NR_CLK, + .nr_clk_ids = CLKS_NR_APOLLO, .clk_regs = apollo_clk_regs, .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs), }; @@ -3938,7 +3961,7 @@ static const struct samsung_cmu_info atlas_cmu_info __initconst = { .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks), .cpu_clks = atlas_cpu_clks, .nr_cpu_clks = ARRAY_SIZE(atlas_cpu_clks), - .nr_clk_ids = ATLAS_NR_CLK, + .nr_clk_ids = CLKS_NR_ATLAS, .clk_regs = atlas_clk_regs, .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs), }; @@ -4112,7 +4135,7 @@ static const struct samsung_cmu_info mscl_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(mscl_div_clks), .gate_clks = mscl_gate_clks, .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), - .nr_clk_ids = MSCL_NR_CLK, + .nr_clk_ids = CLKS_NR_MSCL, .clk_regs = mscl_clk_regs, .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), .suspend_regs = mscl_suspend_regs, @@ -4220,7 +4243,7 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(mfc_div_clks), .gate_clks = mfc_gate_clks, .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), - .nr_clk_ids = MFC_NR_CLK, + .nr_clk_ids = CLKS_NR_MFC, .clk_regs = mfc_clk_regs, .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), .suspend_regs = mfc_suspend_regs, @@ -4330,7 +4353,7 @@ static const struct samsung_cmu_info hevc_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(hevc_div_clks), .gate_clks = hevc_gate_clks, .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks), - .nr_clk_ids = HEVC_NR_CLK, + .nr_clk_ids = CLKS_NR_HEVC, .clk_regs = hevc_clk_regs, .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs), .suspend_regs = hevc_suspend_regs, @@ -4583,7 +4606,7 @@ static const struct samsung_cmu_info isp_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(isp_div_clks), .gate_clks = isp_gate_clks, .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), - .nr_clk_ids = ISP_NR_CLK, + .nr_clk_ids = CLKS_NR_ISP, .clk_regs = isp_clk_regs, .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), .suspend_regs = isp_suspend_regs, @@ -5065,7 +5088,7 @@ static const struct samsung_cmu_info cam0_cmu_info __initconst = { .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks), .fixed_clks = cam0_fixed_clks, .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks), - .nr_clk_ids = CAM0_NR_CLK, + .nr_clk_ids = CLKS_NR_CAM0, .clk_regs = cam0_clk_regs, .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs), .suspend_regs = cam0_suspend_regs, @@ -5440,7 +5463,7 @@ static const struct samsung_cmu_info cam1_cmu_info __initconst = { .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks), .fixed_clks = cam1_fixed_clks, .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks), - .nr_clk_ids = CAM1_NR_CLK, + .nr_clk_ids = CLKS_NR_CAM1, .clk_regs = cam1_clk_regs, .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs), .suspend_regs = cam1_suspend_regs, @@ -5472,7 +5495,7 @@ static const struct samsung_gate_clock imem_gate_clks[] __initconst = { static const struct samsung_cmu_info imem_cmu_info __initconst = { .gate_clks = imem_gate_clks, .nr_gate_clks = ARRAY_SIZE(imem_gate_clks), - .nr_clk_ids = IMEM_NR_CLK, + .nr_clk_ids = CLKS_NR_IMEM, .clk_regs = imem_clk_regs, .nr_clk_regs = ARRAY_SIZE(imem_clk_regs), .clk_name = "aclk_imem_200", From ef4923c8e0523d83b7cd4918760e03b03b2b08ad Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:35 +0200 Subject: [PATCH 24/37] clk: samsung: exynos7885: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-9-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos7885.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c index 0d2a950ed184..5d58879606ee 100644 --- a/drivers/clk/samsung/clk-exynos7885.c +++ b/drivers/clk/samsung/clk-exynos7885.c @@ -17,6 +17,12 @@ #include "clk.h" #include "clk-exynos-arm64.h" +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1) +#define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1) +#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1) +#define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1) + /* ---- CMU_TOP ------------------------------------------------------------- */ /* Register Offset definitions for CMU_TOP (0x12060000) */ @@ -334,7 +340,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(top_div_clks), .gate_clks = top_gate_clks, .nr_gate_clks = ARRAY_SIZE(top_gate_clks), - .nr_clk_ids = TOP_NR_CLK, + .nr_clk_ids = CLKS_NR_TOP, .clk_regs = top_clk_regs, .nr_clk_regs = ARRAY_SIZE(top_clk_regs), }; @@ -553,7 +559,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), .gate_clks = peri_gate_clks, .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), - .nr_clk_ids = PERI_NR_CLK, + .nr_clk_ids = CLKS_NR_PERI, .clk_regs = peri_clk_regs, .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), .clk_name = "dout_peri_bus", @@ -662,7 +668,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(core_div_clks), .gate_clks = core_gate_clks, .nr_gate_clks = ARRAY_SIZE(core_gate_clks), - .nr_clk_ids = CORE_NR_CLK, + .nr_clk_ids = CLKS_NR_CORE, .clk_regs = core_clk_regs, .nr_clk_regs = ARRAY_SIZE(core_clk_regs), .clk_name = "dout_core_bus", @@ -744,7 +750,7 @@ static const struct samsung_cmu_info fsys_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), .gate_clks = fsys_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), - .nr_clk_ids = FSYS_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS, .clk_regs = fsys_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), .clk_name = "dout_fsys_bus", From 56d62cd46dee861080e2484e1bdcc9f892add060 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:36 +0200 Subject: [PATCH 25/37] clk: samsung: exynos850: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Sam Protsenko Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-10-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos850.c | 35 ++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index 98b23af7324d..a6b12ce1211e 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -17,6 +17,19 @@ #include "clk.h" #include "clk-exynos-arm64.h" +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1) +#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1) +#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1) +#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1) +#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1) +#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1) +#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1) +#define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1) +#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1) +#define CLKS_NR_CORE (CLK_GOUT_SYSREG_CORE_PCLK + 1) +#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1) + /* ---- CMU_TOP ------------------------------------------------------------- */ /* Register Offset definitions for CMU_TOP (0x120e0000) */ @@ -486,7 +499,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(top_div_clks), .gate_clks = top_gate_clks, .nr_gate_clks = ARRAY_SIZE(top_gate_clks), - .nr_clk_ids = TOP_NR_CLK, + .nr_clk_ids = CLKS_NR_TOP, .clk_regs = top_clk_regs, .nr_clk_regs = ARRAY_SIZE(top_clk_regs), }; @@ -626,7 +639,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = { .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), .fixed_clks = apm_fixed_clks, .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), - .nr_clk_ids = APM_NR_CLK, + .nr_clk_ids = CLKS_NR_APM, .clk_regs = apm_clk_regs, .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), .clk_name = "dout_clkcmu_apm_bus", @@ -909,7 +922,7 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = { .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), .fixed_clks = aud_fixed_clks, .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), - .nr_clk_ids = AUD_NR_CLK, + .nr_clk_ids = CLKS_NR_AUD, .clk_regs = aud_clk_regs, .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), .clk_name = "dout_aud", @@ -1012,7 +1025,7 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = { .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks), .fixed_clks = cmgp_fixed_clks, .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks), - .nr_clk_ids = CMGP_NR_CLK, + .nr_clk_ids = CLKS_NR_CMGP, .clk_regs = cmgp_clk_regs, .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), .clk_name = "gout_clkcmu_cmgp_bus", @@ -1108,7 +1121,7 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(g3d_div_clks), .gate_clks = g3d_gate_clks, .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), - .nr_clk_ids = G3D_NR_CLK, + .nr_clk_ids = CLKS_NR_G3D, .clk_regs = g3d_clk_regs, .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), .clk_name = "dout_g3d_switch", @@ -1210,7 +1223,7 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), .gate_clks = hsi_gate_clks, .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), - .nr_clk_ids = HSI_NR_CLK, + .nr_clk_ids = CLKS_NR_HSI, .clk_regs = hsi_clk_regs, .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), .clk_name = "dout_hsi_bus", @@ -1342,7 +1355,7 @@ static const struct samsung_cmu_info is_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(is_div_clks), .gate_clks = is_gate_clks, .nr_gate_clks = ARRAY_SIZE(is_gate_clks), - .nr_clk_ids = IS_NR_CLK, + .nr_clk_ids = CLKS_NR_IS, .clk_regs = is_clk_regs, .nr_clk_regs = ARRAY_SIZE(is_clk_regs), .clk_name = "dout_is_bus", @@ -1451,7 +1464,7 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks), .gate_clks = mfcmscl_gate_clks, .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks), - .nr_clk_ids = MFCMSCL_NR_CLK, + .nr_clk_ids = CLKS_NR_MFCMSCL, .clk_regs = mfcmscl_clk_regs, .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs), .clk_name = "dout_mfcmscl_mfc", @@ -1626,7 +1639,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(peri_div_clks), .gate_clks = peri_gate_clks, .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), - .nr_clk_ids = PERI_NR_CLK, + .nr_clk_ids = CLKS_NR_PERI, .clk_regs = peri_clk_regs, .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), .clk_name = "dout_peri_bus", @@ -1733,7 +1746,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(core_div_clks), .gate_clks = core_gate_clks, .nr_gate_clks = ARRAY_SIZE(core_gate_clks), - .nr_clk_ids = CORE_NR_CLK, + .nr_clk_ids = CLKS_NR_CORE, .clk_regs = core_clk_regs, .nr_clk_regs = ARRAY_SIZE(core_clk_regs), .clk_name = "dout_core_bus", @@ -1807,7 +1820,7 @@ static const struct samsung_cmu_info dpu_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(dpu_div_clks), .gate_clks = dpu_gate_clks, .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), - .nr_clk_ids = DPU_NR_CLK, + .nr_clk_ids = CLKS_NR_DPU, .clk_regs = dpu_clk_regs, .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), .clk_name = "dout_dpu", From 901a0c690f547dbe24fd599e7fc58d7cbf69599b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:37 +0200 Subject: [PATCH 26/37] clk: samsung: exynoautov9: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-11-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynosautov9.c | 29 ++++++++++++++++++-------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c index 7b16320bba66..0715fce81f64 100644 --- a/drivers/clk/samsung/clk-exynosautov9.c +++ b/drivers/clk/samsung/clk-exynosautov9.c @@ -18,6 +18,17 @@ #include "clk.h" #include "clk-exynos-arm64.h" +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1) +#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1) +#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1) +#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1) +#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1) +#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1) +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_PCLK_11 + 1) +#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_PCLK_11 + 1) +#define CLKS_NR_PERIS (CLK_GOUT_WDT_CLUSTER1 + 1) + /* ---- CMU_TOP ------------------------------------------------------------ */ /* Register Offset definitions for CMU_TOP (0x1b240000) */ @@ -943,7 +954,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), .gate_clks = top_gate_clks, .nr_gate_clks = ARRAY_SIZE(top_gate_clks), - .nr_clk_ids = TOP_NR_CLK, + .nr_clk_ids = CLKS_NR_TOP, .clk_regs = top_clk_regs, .nr_clk_regs = ARRAY_SIZE(top_clk_regs), }; @@ -1003,7 +1014,7 @@ static const struct samsung_cmu_info busmc_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(busmc_div_clks), .gate_clks = busmc_gate_clks, .nr_gate_clks = ARRAY_SIZE(busmc_gate_clks), - .nr_clk_ids = BUSMC_NR_CLK, + .nr_clk_ids = CLKS_NR_BUSMC, .clk_regs = busmc_clk_regs, .nr_clk_regs = ARRAY_SIZE(busmc_clk_regs), .clk_name = "dout_clkcmu_busmc_bus", @@ -1061,7 +1072,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(core_div_clks), .gate_clks = core_gate_clks, .nr_gate_clks = ARRAY_SIZE(core_gate_clks), - .nr_clk_ids = CORE_NR_CLK, + .nr_clk_ids = CLKS_NR_CORE, .clk_regs = core_clk_regs, .nr_clk_regs = ARRAY_SIZE(core_clk_regs), .clk_name = "dout_clkcmu_core_bus", @@ -1301,7 +1312,7 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), .gate_clks = fsys0_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), - .nr_clk_ids = FSYS0_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS0, .clk_regs = fsys0_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), .clk_name = "dout_clkcmu_fsys0_bus", @@ -1428,7 +1439,7 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), .gate_clks = fsys1_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), - .nr_clk_ids = FSYS1_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS1, .clk_regs = fsys1_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), .clk_name = "dout_clkcmu_fsys1_bus", @@ -1495,7 +1506,7 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks), .gate_clks = fsys2_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks), - .nr_clk_ids = FSYS2_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS2, .clk_regs = fsys2_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs), .clk_name = "dout_clkcmu_fsys2_bus", @@ -1750,7 +1761,7 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(peric0_div_clks), .gate_clks = peric0_gate_clks, .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), - .nr_clk_ids = PERIC0_NR_CLK, + .nr_clk_ids = CLKS_NR_PERIC0, .clk_regs = peric0_clk_regs, .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), .clk_name = "dout_clkcmu_peric0_bus", @@ -2005,7 +2016,7 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(peric1_div_clks), .gate_clks = peric1_gate_clks, .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), - .nr_clk_ids = PERIC1_NR_CLK, + .nr_clk_ids = CLKS_NR_PERIC1, .clk_regs = peric1_clk_regs, .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), .clk_name = "dout_clkcmu_peric1_bus", @@ -2052,7 +2063,7 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), .gate_clks = peris_gate_clks, .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), - .nr_clk_ids = PERIS_NR_CLK, + .nr_clk_ids = CLKS_NR_PERIS, .clk_regs = peris_clk_regs, .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), .clk_name = "dout_clkcmu_peris_bus", From b3f9581affb03ed28ff1905b649e66904f29b9e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:38 +0200 Subject: [PATCH 27/37] dt-bindings: clock: samsung: remove define with number of clocks Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Remove it entirely from the bindings, once Linux drivers stopped using them. Reviewed-by: Conor Dooley Reviewed-by: Sam Protsenko Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-12-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/clock/exynos3250.h | 18 -------- include/dt-bindings/clock/exynos4.h | 5 --- include/dt-bindings/clock/exynos5250.h | 3 -- include/dt-bindings/clock/exynos5260-clk.h | 25 ----------- include/dt-bindings/clock/exynos5410.h | 2 - include/dt-bindings/clock/exynos5420.h | 3 -- include/dt-bindings/clock/exynos5433.h | 42 ------------------- include/dt-bindings/clock/exynos7885.h | 4 -- include/dt-bindings/clock/exynos850.h | 10 ----- .../dt-bindings/clock/samsung,exynosautov9.h | 18 -------- 10 files changed, 130 deletions(-) diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index fe8214017b46..cc7268151843 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -256,12 +256,6 @@ #define CLK_SCLK_UART2 248 #define CLK_SCLK_MMC2 249 -/* - * Total number of clocks of main CMU. - * NOTE: Must be equal to last clock ID increased by one. - */ -#define CLK_NR_CLKS 250 - /* * CMU DMC */ @@ -283,12 +277,6 @@ #define CLK_DIV_DMCP 19 #define CLK_DIV_DMCD 20 -/* - * Total number of clocks of main CMU. - * NOTE: Must be equal to last clock ID increased by one. - */ -#define NR_CLKS_DMC 21 - /* * CMU ISP */ @@ -344,10 +332,4 @@ #define CLK_ASYNCAXIM 46 #define CLK_SCLK_MPWM_ISP 47 -/* - * Total number of clocks of CMU_ISP. - * NOTE: Must be equal to last clock ID increased by one. - */ -#define NR_CLKS_ISP 48 - #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index acbfbab875ec..4ebff79ed9e2 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -239,9 +239,6 @@ #define CLK_DIV_GDR 460 #define CLK_DIV_CORE2 461 -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 462 - /* Exynos4x12 ISP clocks */ #define CLK_ISP_FIMC_ISP 1 #define CLK_ISP_FIMC_DRC 2 @@ -275,6 +272,4 @@ #define CLK_ISP_DIV_MCUISP0 29 #define CLK_ISP_DIV_MCUISP1 30 -#define CLK_NR_ISP_CLKS 31 - #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h index 4680da7357d3..2337c028bbe1 100644 --- a/include/dt-bindings/clock/exynos5250.h +++ b/include/dt-bindings/clock/exynos5250.h @@ -177,7 +177,4 @@ #define CLK_MOUT_MPLL 1029 #define CLK_MOUT_VPLLSRC 1030 -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 1031 - #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ diff --git a/include/dt-bindings/clock/exynos5260-clk.h b/include/dt-bindings/clock/exynos5260-clk.h index 98a58cbd81b2..dfde40ea40f0 100644 --- a/include/dt-bindings/clock/exynos5260-clk.h +++ b/include/dt-bindings/clock/exynos5260-clk.h @@ -137,8 +137,6 @@ #define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122 #define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123 #define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124 -#define TOP_NR_CLK 125 - /* List Of Clocks For CMU_EGL */ @@ -153,8 +151,6 @@ #define EGL_DOUT_ACLK_EGL 9 #define EGL_DOUT_EGL2 10 #define EGL_DOUT_EGL1 11 -#define EGL_NR_CLK 12 - /* List Of Clocks For CMU_KFC */ @@ -168,8 +164,6 @@ #define KFC_DOUT_KFC_ATCLK 8 #define KFC_DOUT_KFC2 9 #define KFC_DOUT_KFC1 10 -#define KFC_NR_CLK 11 - /* List Of Clocks For CMU_MIF */ @@ -200,8 +194,6 @@ #define MIF_CLK_INTMEM 25 #define MIF_SCLK_LPDDR3PHY_WRAP_U1 26 #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 -#define MIF_NR_CLK 28 - /* List Of Clocks For CMU_G3D */ @@ -211,8 +203,6 @@ #define G3D_DOUT_ACLK_G3D 4 #define G3D_CLK_G3D_HPM 5 #define G3D_CLK_G3D 6 -#define G3D_NR_CLK 7 - /* List Of Clocks For CMU_AUD */ @@ -231,8 +221,6 @@ #define AUD_SCLK_AUD_UART 13 #define AUD_SCLK_PCM 14 #define AUD_SCLK_I2S 15 -#define AUD_NR_CLK 16 - /* List Of Clocks For CMU_MFC */ @@ -241,8 +229,6 @@ #define MFC_CLK_MFC 3 #define MFC_CLK_SMMU2_MFCM1 4 #define MFC_CLK_SMMU2_MFCM0 5 -#define MFC_NR_CLK 6 - /* List Of Clocks For CMU_GSCL */ @@ -272,8 +258,6 @@ #define GSCL_CLK_SMMU3_MSCL1 24 #define GSCL_SCLK_CSIS1_WRAP 25 #define GSCL_SCLK_CSIS0_WRAP 26 -#define GSCL_NR_CLK 27 - /* List Of Clocks For CMU_FSYS */ @@ -295,8 +279,6 @@ #define FSYS_CLK_SMMU_RTIC 16 #define FSYS_PHYCLK_USBDRD30 17 #define FSYS_PHYCLK_USBHOST20 18 -#define FSYS_NR_CLK 19 - /* List Of Clocks For CMU_PERI */ @@ -366,8 +348,6 @@ #define PERI_SCLK_SPDIF 64 #define PERI_SCLK_I2S 65 #define PERI_SCLK_PCM1 66 -#define PERI_NR_CLK 67 - /* List Of Clocks For CMU_DISP */ @@ -406,8 +386,6 @@ #define DISP_CLK_DP 33 #define DISP_SCLK_PIXEL 34 #define DISP_MOUT_HDMI_PHY_PIXEL_USER 35 -#define DISP_NR_CLK 36 - /* List Of Clocks For CMU_G2D */ @@ -423,8 +401,6 @@ #define G2D_CLK_SMMU_SSS 10 #define G2D_CLK_SMMU_MDMA 11 #define G2D_CLK_SMMU3_G2D 12 -#define G2D_NR_CLK 13 - /* List Of Clocks For CMU_ISP */ @@ -461,6 +437,5 @@ #define ISP_SCLK_SPI0_EXT 31 #define ISP_SCLK_SPI1_EXT 32 #define ISP_SCLK_UART_EXT 33 -#define ISP_NR_CLK 34 #endif diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 86c2ad56c5ef..7a1a93f8df6c 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -61,6 +61,4 @@ #define CLK_USBD301 367 #define CLK_SSS 471 -#define CLK_NR_CLKS 512 - #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 9fffc6ceaadd..73e82527a9e9 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -271,7 +271,4 @@ #define CLK_DOUT_PCLK_DREX0 798 #define CLK_DOUT_PCLK_DREX1 799 -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 800 - #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 25ffa53573a5..d12c1a963fa1 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -188,8 +188,6 @@ #define CLK_SCLK_ISP_SPI0_CAM1 252 #define CLK_SCLK_HDMI_SPDIF_DISP 253 -#define TOP_NR_CLK 254 - /* CMU_CPIF */ #define CLK_FOUT_MPHY_PLL 1 @@ -200,8 +198,6 @@ #define CLK_SCLK_MPHY_PLL 11 #define CLK_SCLK_UFS_MPHY 11 -#define CPIF_NR_CLK 12 - /* CMU_MIF */ #define CLK_FOUT_MEM0_PLL 1 #define CLK_FOUT_MEM1_PLL 2 @@ -396,8 +392,6 @@ #define CLK_SCLK_BUS_PLL_APOLLO 199 #define CLK_SCLK_BUS_PLL_ATLAS 200 -#define MIF_NR_CLK 201 - /* CMU_PERIC */ #define CLK_PCLK_SPI2 1 #define CLK_PCLK_SPI1 2 @@ -468,8 +462,6 @@ #define CLK_DIV_SCLK_SCI 70 #define CLK_DIV_SCLK_SC_IN 71 -#define PERIC_NR_CLK 72 - /* CMU_PERIS */ #define CLK_PCLK_HPM_APBIF 1 #define CLK_PCLK_TMU1_APBIF 2 @@ -513,8 +505,6 @@ #define CLK_SCLK_ANTIRBK_CNT 40 #define CLK_SCLK_OTP_CON 41 -#define PERIS_NR_CLK 42 - /* CMU_FSYS */ #define CLK_MOUT_ACLK_FSYS_200_USER 1 #define CLK_MOUT_SCLK_MMC2_USER 2 @@ -621,8 +611,6 @@ #define CLK_SCLK_USBDRD30 114 #define CLK_PCIE 115 -#define FSYS_NR_CLK 116 - /* CMU_G2D */ #define CLK_MUX_ACLK_G2D_266_USER 1 #define CLK_MUX_ACLK_G2D_400_USER 2 @@ -653,8 +641,6 @@ #define CLK_PCLK_G2D 25 #define CLK_PCLK_SMMU_G2D 26 -#define G2D_NR_CLK 27 - /* CMU_DISP */ #define CLK_FOUT_DISP_PLL 1 @@ -771,8 +757,6 @@ #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 -#define DISP_NR_CLK 116 - /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1 #define CLK_MOUT_SCLK_AUD_PCM 2 @@ -824,8 +808,6 @@ #define CLK_SCLK_I2S_BCLK 46 #define CLK_SCLK_AUD_I2S 47 -#define AUD_NR_CLK 48 - /* CMU_BUS{0|1|2} */ #define CLK_DIV_PCLK_BUS_133 1 @@ -840,8 +822,6 @@ #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ -#define BUSx_NR_CLK 11 - /* CMU_G3D */ #define CLK_FOUT_G3D_PLL 1 @@ -865,8 +845,6 @@ #define CLK_PCLK_SYSREG_G3D 18 #define CLK_SCLK_HPM_G3D 19 -#define G3D_NR_CLK 20 - /* CMU_GSCL */ #define CLK_MOUT_ACLK_GSCL_111_USER 1 #define CLK_MOUT_ACLK_GSCL_333_USER 2 @@ -898,8 +876,6 @@ #define CLK_PCLK_SMMU_GSCL1 27 #define CLK_PCLK_SMMU_GSCL2 28 -#define GSCL_NR_CLK 29 - /* CMU_APOLLO */ #define CLK_FOUT_APOLLO_PLL 1 @@ -935,8 +911,6 @@ #define CLK_SCLK_HPM_APOLLO 29 #define CLK_SCLK_APOLLO 30 -#define APOLLO_NR_CLK 31 - /* CMU_ATLAS */ #define CLK_FOUT_ATLAS_PLL 1 @@ -981,8 +955,6 @@ #define CLK_ATCLK 38 #define CLK_SCLK_ATLAS 39 -#define ATLAS_NR_CLK 40 - /* CMU_MSCL */ #define CLK_MOUT_SCLK_JPEG_USER 1 #define CLK_MOUT_ACLK_MSCL_400_USER 2 @@ -1016,8 +988,6 @@ #define CLK_PCLK_SMMU_JPEG 28 #define CLK_SCLK_JPEG 29 -#define MSCL_NR_CLK 30 - /* CMU_MFC */ #define CLK_MOUT_ACLK_MFC_400_USER 1 @@ -1040,8 +1010,6 @@ #define CLK_PCLK_SMMU_MFC_1 17 #define CLK_PCLK_SMMU_MFC_0 18 -#define MFC_NR_CLK 19 - /* CMU_HEVC */ #define CLK_MOUT_ACLK_HEVC_400_USER 1 @@ -1064,8 +1032,6 @@ #define CLK_PCLK_SMMU_HEVC_1 17 #define CLK_PCLK_SMMU_HEVC_0 18 -#define HEVC_NR_CLK 19 - /* CMU_ISP */ #define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 #define CLK_MOUT_ACLK_ISP_400_USER 2 @@ -1147,8 +1113,6 @@ #define CLK_SCLK_PIXELASYNCS_ISPC 76 #define CLK_SCLK_PIXELASYNCM_ISPC 77 -#define ISP_NR_CLK 78 - /* CMU_CAM0 */ #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1 #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2 @@ -1285,8 +1249,6 @@ #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132 #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133 -#define CAM0_NR_CLK 134 - /* CMU_CAM1 */ #define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1 @@ -1404,12 +1366,8 @@ #define CLK_ATCLK_ISP 111 #define CLK_SCLK_ISP_CA5 112 -#define CAM1_NR_CLK 113 - /* CMU_IMEM */ #define CLK_ACLK_SLIMSSS 2 #define CLK_PCLK_SLIMSSS 35 -#define IMEM_NR_CLK 36 - #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h index 8256e7430b63..255e3aa94323 100644 --- a/include/dt-bindings/clock/exynos7885.h +++ b/include/dt-bindings/clock/exynos7885.h @@ -69,7 +69,6 @@ #define CLK_GOUT_FSYS_MMC_EMBD 58 #define CLK_GOUT_FSYS_MMC_SDIO 59 #define CLK_GOUT_FSYS_USB30DRD 60 -#define TOP_NR_CLK 61 /* CMU_CORE */ #define CLK_MOUT_CORE_BUS_USER 1 @@ -86,7 +85,6 @@ #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12 #define CLK_GOUT_TREX_P_CORE_PCLK 13 #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14 -#define CORE_NR_CLK 15 /* CMU_PERI */ #define CLK_MOUT_PERI_BUS_USER 1 @@ -132,7 +130,6 @@ #define CLK_GOUT_SYSREG_PERI_PCLK 41 #define CLK_GOUT_WDT0_PCLK 42 #define CLK_GOUT_WDT1_PCLK 43 -#define PERI_NR_CLK 44 /* CMU_FSYS */ #define CLK_MOUT_FSYS_BUS_USER 1 @@ -146,6 +143,5 @@ #define CLK_GOUT_MMC_EMBD_SDCLKIN 8 #define CLK_GOUT_MMC_SDIO_ACLK 9 #define CLK_GOUT_MMC_SDIO_SDCLKIN 10 -#define FSYS_NR_CLK 11 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index afacba338c91..3090e09c9a55 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -88,7 +88,6 @@ #define CLK_MOUT_G3D_SWITCH 76 #define CLK_GOUT_G3D_SWITCH 77 #define CLK_DOUT_G3D_SWITCH 78 -#define TOP_NR_CLK 79 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -115,7 +114,6 @@ #define CLK_GOUT_GPIO_ALIVE_PCLK 22 #define CLK_GOUT_PMU_ALIVE_PCLK 23 #define CLK_GOUT_SYSREG_APM_PCLK 24 -#define APM_NR_CLK 25 /* CMU_AUD */ #define CLK_DOUT_AUD_AUDIF 1 @@ -179,7 +177,6 @@ #define IOCLK_AUDIOCDCLK6 59 #define TICK_USB 60 #define CLK_GOUT_AUD_CMU_AUD_PCLK 61 -#define AUD_NR_CLK 62 /* CMU_CMGP */ #define CLK_RCO_CMGP 1 @@ -197,7 +194,6 @@ #define CLK_GOUT_CMGP_USI1_IPCLK 13 #define CLK_GOUT_CMGP_USI1_PCLK 14 #define CLK_GOUT_SYSREG_CMGP_PCLK 15 -#define CMGP_NR_CLK 16 /* CMU_G3D */ #define CLK_FOUT_G3D_PLL 1 @@ -212,7 +208,6 @@ #define CLK_GOUT_G3D_BUSD_CLK 10 #define CLK_GOUT_G3D_BUSP_CLK 11 #define CLK_GOUT_G3D_SYSREG_PCLK 12 -#define G3D_NR_CLK 13 /* CMU_HSI */ #define CLK_MOUT_HSI_BUS_USER 1 @@ -231,7 +226,6 @@ #define CLK_GOUT_HSI_PPMU_ACLK 14 #define CLK_GOUT_HSI_PPMU_PCLK 15 #define CLK_GOUT_HSI_CMU_HSI_PCLK 16 -#define HSI_NR_CLK 17 /* CMU_IS */ #define CLK_MOUT_IS_BUS_USER 1 @@ -257,7 +251,6 @@ #define CLK_GOUT_IS_SYSMMU_IS0_CLK 21 #define CLK_GOUT_IS_SYSMMU_IS1_CLK 22 #define CLK_GOUT_IS_SYSREG_PCLK 23 -#define IS_NR_CLK 24 /* CMU_MFCMSCL */ #define CLK_MOUT_MFCMSCL_MFC_USER 1 @@ -275,7 +268,6 @@ #define CLK_GOUT_MFCMSCL_PPMU_PCLK 13 #define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14 #define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15 -#define MFCMSCL_NR_CLK 16 /* CMU_PERI */ #define CLK_MOUT_PERI_BUS_USER 1 @@ -312,7 +304,6 @@ #define CLK_GOUT_UART_PCLK 32 #define CLK_GOUT_WDT0_PCLK 33 #define CLK_GOUT_WDT1_PCLK 34 -#define PERI_NR_CLK 35 /* CMU_CORE */ #define CLK_MOUT_CORE_BUS_USER 1 @@ -329,7 +320,6 @@ #define CLK_GOUT_SSS_PCLK 12 #define CLK_GOUT_GPIO_CORE_PCLK 13 #define CLK_GOUT_SYSREG_CORE_PCLK 14 -#define CORE_NR_CLK 15 /* CMU_DPU */ #define CLK_MOUT_DPU_USER 1 diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h index 42133af6d6b9..3065375c2d8b 100644 --- a/include/dt-bindings/clock/samsung,exynosautov9.h +++ b/include/dt-bindings/clock/samsung,exynosautov9.h @@ -166,16 +166,12 @@ #define GOUT_CLKCMU_PERIC1_IP 248 #define GOUT_CLKCMU_PERIS_BUS 249 -#define TOP_NR_CLK 250 - /* CMU_BUSMC */ #define CLK_MOUT_BUSMC_BUS_USER 1 #define CLK_DOUT_BUSMC_BUSP 2 #define CLK_GOUT_BUSMC_PDMA0_PCLK 3 #define CLK_GOUT_BUSMC_SPDMA_PCLK 4 -#define BUSMC_NR_CLK 5 - /* CMU_CORE */ #define CLK_MOUT_CORE_BUS_USER 1 #define CLK_DOUT_CORE_BUSP 2 @@ -183,8 +179,6 @@ #define CLK_GOUT_CORE_CCI_PCLK 4 #define CLK_GOUT_CORE_CMU_CORE_PCLK 5 -#define CORE_NR_CLK 6 - /* CMU_FSYS0 */ #define CLK_MOUT_FSYS0_BUS_USER 1 #define CLK_MOUT_FSYS0_PCIE_USER 2 @@ -226,8 +220,6 @@ #define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35 #define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36 -#define FSYS0_NR_CLK 37 - /* CMU_FSYS1 */ #define FOUT_MMC_PLL 1 @@ -251,8 +243,6 @@ #define CLK_GOUT_FSYS1_USB30_0_ACLK 17 #define CLK_GOUT_FSYS1_USB30_1_ACLK 18 -#define FSYS1_NR_CLK 19 - /* CMU_FSYS2 */ #define CLK_MOUT_FSYS2_BUS_USER 1 #define CLK_MOUT_FSYS2_UFS_EMBD_USER 2 @@ -262,8 +252,6 @@ #define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6 #define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7 -#define FSYS2_NR_CLK 8 - /* CMU_PERIC0 */ #define CLK_MOUT_PERIC0_BUS_USER 1 #define CLK_MOUT_PERIC0_IP_USER 2 @@ -308,8 +296,6 @@ #define CLK_GOUT_PERIC0_PCLK_10 42 #define CLK_GOUT_PERIC0_PCLK_11 43 -#define PERIC0_NR_CLK 44 - /* CMU_PERIC1 */ #define CLK_MOUT_PERIC1_BUS_USER 1 #define CLK_MOUT_PERIC1_IP_USER 2 @@ -354,14 +340,10 @@ #define CLK_GOUT_PERIC1_PCLK_10 42 #define CLK_GOUT_PERIC1_PCLK_11 43 -#define PERIC1_NR_CLK 44 - /* CMU_PERIS */ #define CLK_MOUT_PERIS_BUS_USER 1 #define CLK_GOUT_SYSREG_PERIS_PCLK 2 #define CLK_GOUT_WDT_CLUSTER0 3 #define CLK_GOUT_WDT_CLUSTER1 4 -#define PERIS_NR_CLK 5 - #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */ From f316cdff8d677db9ad9c90acb44c4cd535b0ee27 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 17 Aug 2023 13:30:22 -0700 Subject: [PATCH 28/37] clk: Annotate struct clk_hw_onecell_data with __counted_by Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct clk_hw_onecell_data. Additionally, since the element count member must be set before accessing the annotated flexible array member, move its initialization earlier. [1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci Cc: Michael Turquette Cc: Stephen Boyd Cc: Joel Stanley Cc: Andrew Jeffery Cc: Taichi Sugaya Cc: Takao Orito Cc: Qin Jian Cc: Andrew Lunn Cc: Gregory Clement Cc: Sebastian Hesselbarth Cc: Andy Gross Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: Sergio Paracuellos Cc: Matthias Brugger Cc: AngeloGioacchino Del Regno Cc: Maxime Ripard Cc: Chen-Yu Tsai Cc: Jernej Skrabec Cc: David Airlie Cc: Daniel Vetter Cc: Samuel Holland Cc: Vinod Koul Cc: Kishon Vijay Abraham I Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-mediatek@lists.infradead.org Cc: dri-devel@lists.freedesktop.org Cc: linux-sunxi@lists.linux.dev Cc: linux-phy@lists.infradead.org Signed-off-by: Kees Cook Link: https://lore.kernel.org/r/20230817203019.never.795-kees@kernel.org Reviewed-by: Gustavo A. R. Silva Signed-off-by: Stephen Boyd --- drivers/clk/clk-aspeed.c | 3 +-- drivers/clk/clk-ast2600.c | 2 +- drivers/clk/clk-gemini.c | 2 +- drivers/clk/clk-milbeaut.c | 3 +-- drivers/clk/clk-sp7021.c | 3 +-- drivers/clk/mvebu/cp110-system-controller.c | 2 +- drivers/clk/qcom/clk-cpu-8996.c | 2 +- drivers/clk/ralink/clk-mt7621.c | 3 +-- drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 3 +-- drivers/phy/qualcomm/phy-qcom-edp.c | 2 +- include/linux/clk-provider.h | 2 +- 11 files changed, 11 insertions(+), 16 deletions(-) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 411ff5fb2c07..b42fc74b8f2a 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -701,6 +701,7 @@ static void __init aspeed_cc_init(struct device_node *np) GFP_KERNEL); if (!aspeed_clk_data) return; + aspeed_clk_data->num = ASPEED_NUM_CLKS; /* * This way all clocks fetched before the platform device probes, @@ -732,8 +733,6 @@ static void __init aspeed_cc_init(struct device_node *np) aspeed_ast2500_cc(map); else pr_err("unknown platform, failed to add clocks\n"); - - aspeed_clk_data->num = ASPEED_NUM_CLKS; ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); if (ret) pr_err("failed to add DT provider: %d\n", ret); diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index a094a2601a37..df464ae95ff3 100644 --- a/drivers/clk/clk-ast2600.c +++ b/drivers/clk/clk-ast2600.c @@ -839,6 +839,7 @@ static void __init aspeed_g6_cc_init(struct device_node *np) ASPEED_G6_NUM_CLKS), GFP_KERNEL); if (!aspeed_g6_clk_data) return; + aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS; /* * This way all clocks fetched before the platform device probes, @@ -860,7 +861,6 @@ static void __init aspeed_g6_cc_init(struct device_node *np) } aspeed_g6_cc(map); - aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS; ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data); if (ret) pr_err("failed to add DT provider: %d\n", ret); diff --git a/drivers/clk/clk-gemini.c b/drivers/clk/clk-gemini.c index a23fa6d47ef1..2572d15aadd0 100644 --- a/drivers/clk/clk-gemini.c +++ b/drivers/clk/clk-gemini.c @@ -404,6 +404,7 @@ static void __init gemini_cc_init(struct device_node *np) GFP_KERNEL); if (!gemini_clk_data) return; + gemini_clk_data->num = GEMINI_NUM_CLKS; /* * This way all clock fetched before the platform device probes, @@ -457,7 +458,6 @@ static void __init gemini_cc_init(struct device_node *np) gemini_clk_data->hws[GEMINI_CLK_APB] = hw; /* Register the clocks to be accessed by the device tree */ - gemini_clk_data->num = GEMINI_NUM_CLKS; of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data); } CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init); diff --git a/drivers/clk/clk-milbeaut.c b/drivers/clk/clk-milbeaut.c index 050fd4fb588f..18c20aff45f7 100644 --- a/drivers/clk/clk-milbeaut.c +++ b/drivers/clk/clk-milbeaut.c @@ -618,6 +618,7 @@ static void __init m10v_cc_init(struct device_node *np) if (!m10v_clk_data) return; + m10v_clk_data->num = M10V_NUM_CLKS; base = of_iomap(np, 0); if (!base) { @@ -654,8 +655,6 @@ static void __init m10v_cc_init(struct device_node *np) base + CLKSEL(1), 0, 3, 0, rclk_table, &m10v_crglock, NULL); m10v_clk_data->hws[M10V_RCLK_ID] = hw; - - m10v_clk_data->num = M10V_NUM_CLKS; of_clk_add_hw_provider(np, of_clk_hw_onecell_get, m10v_clk_data); } CLK_OF_DECLARE_DRIVER(m10v_cc, "socionext,milbeaut-m10v-ccu", m10v_cc_init); diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c index 11d22043ddd7..01d3c4c7b0b2 100644 --- a/drivers/clk/clk-sp7021.c +++ b/drivers/clk/clk-sp7021.c @@ -621,6 +621,7 @@ static int sp7021_clk_probe(struct platform_device *pdev) GFP_KERNEL); if (!clk_data) return -ENOMEM; + clk_data->num = CLK_MAX; hws = clk_data->hws; pd_ext.index = 0; @@ -688,8 +689,6 @@ static int sp7021_clk_probe(struct platform_device *pdev) return PTR_ERR(hws[i]); } - clk_data->num = CLK_MAX; - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c index 84c8900542e4..03c59bf22106 100644 --- a/drivers/clk/mvebu/cp110-system-controller.c +++ b/drivers/clk/mvebu/cp110-system-controller.c @@ -240,9 +240,9 @@ static int cp110_syscon_common_probe(struct platform_device *pdev, GFP_KERNEL); if (!cp110_clk_data) return -ENOMEM; + cp110_clk_data->num = CP110_CLK_NUM; cp110_clks = cp110_clk_data->hws; - cp110_clk_data->num = CP110_CLK_NUM; /* Register the PLL0 which is the root of the hw tree */ pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0"); diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 592c7c3cdeb7..72689448a653 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -590,6 +590,7 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev) data = devm_kzalloc(dev, struct_size(data, hws, 2), GFP_KERNEL); if (!data) return -ENOMEM; + data->num = 2; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -605,7 +606,6 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev) data->hws[0] = &pwrcl_pmux.clkr.hw; data->hws[1] = &perfcl_pmux.clkr.hw; - data->num = 2; return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data); } diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c index d95a33293b0a..92d14350c4b3 100644 --- a/drivers/clk/ralink/clk-mt7621.c +++ b/drivers/clk/ralink/clk-mt7621.c @@ -521,6 +521,7 @@ static int mt7621_clk_probe(struct platform_device *pdev) GFP_KERNEL); if (!clk_data) return -ENOMEM; + clk_data->num = count; for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) clk_data->hws[i] = mt7621_clk_early[i]; @@ -537,8 +538,6 @@ static int mt7621_clk_probe(struct platform_device *pdev) goto unreg_clk_fixed; } - clk_data->num = count; - ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); if (ret) { dev_err(dev, "Couldn't add clk hw provider\n"); diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c index da97682b6835..5258ac1e4f53 100644 --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c @@ -141,6 +141,7 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master, GFP_KERNEL); if (!clk_data) return -ENOMEM; + clk_data->num = CLK_NUM; tcon_top->clk_data = clk_data; spin_lock_init(&tcon_top->reg_lock); @@ -213,8 +214,6 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master, goto err_unregister_gates; } - clk_data->num = CLK_NUM; - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_data); if (ret) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index fc8ca0f3018d..5c4305df7d53 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -746,6 +746,7 @@ static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np) data = devm_kzalloc(edp->dev, struct_size(data, hws, 2), GFP_KERNEL); if (!data) return -ENOMEM; + data->num = 2; snprintf(name, sizeof(name), "%s::link_clk", dev_name(edp->dev)); init.ops = &qcom_edp_dp_link_clk_ops; @@ -765,7 +766,6 @@ static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np) data->hws[0] = &edp->dp_link_hw; data->hws[1] = &edp->dp_pixel_hw; - data->num = 2; return devm_of_clk_add_hw_provider(edp->dev, of_clk_hw_onecell_get, data); } diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 0f0cd01906b4..ec32ec58c59f 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1379,7 +1379,7 @@ struct clk_onecell_data { struct clk_hw_onecell_data { unsigned int num; - struct clk_hw *hws[]; + struct clk_hw *hws[] __counted_by(num); }; #define CLK_OF_DECLARE(name, compat, fn) \ From a5be6db5a2880f9edda0f062a0bb23efd01ece37 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 17 Aug 2023 13:29:42 -0700 Subject: [PATCH 29/37] clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct spmi_pmic_div_clk_cc. [1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci Cc: Bjorn Andersson Cc: Andy Gross Cc: Konrad Dybcio Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Kees Cook Link: https://lore.kernel.org/r/20230817202941.never.657-kees@kernel.org Reviewed-by: Gustavo A. R. Silva Signed-off-by: Stephen Boyd --- drivers/clk/qcom/clk-spmi-pmic-div.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-spmi-pmic-div.c b/drivers/clk/qcom/clk-spmi-pmic-div.c index f846be285f51..f394031eb0e5 100644 --- a/drivers/clk/qcom/clk-spmi-pmic-div.c +++ b/drivers/clk/qcom/clk-spmi-pmic-div.c @@ -177,7 +177,7 @@ static const struct clk_ops clk_spmi_pmic_div_ops = { struct spmi_pmic_div_clk_cc { int nclks; - struct clkdiv clks[]; + struct clkdiv clks[] __counted_by(nclks); }; static struct clk_hw * From 979663c3d273a1b36362186607acfc311b521848 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= Date: Fri, 4 Aug 2023 15:49:32 +0200 Subject: [PATCH 30/37] clk: mmp: Remove old non-OF clock drivers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are no MMP2, PXA168 or PXA910 boards still using board files which would use these drivers, so remove them. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20230804-drop-old-mmp-clk-v1-1-0c07db6cee90@skole.hr Signed-off-by: Stephen Boyd --- drivers/clk/mmp/Makefile | 4 - drivers/clk/mmp/clk-mmp2.c | 454 ----------------------------------- drivers/clk/mmp/clk-pxa168.c | 354 --------------------------- drivers/clk/mmp/clk-pxa910.c | 325 ------------------------- include/linux/clk/mmp.h | 18 -- 5 files changed, 1155 deletions(-) delete mode 100644 drivers/clk/mmp/clk-mmp2.c delete mode 100644 drivers/clk/mmp/clk-pxa168.c delete mode 100644 drivers/clk/mmp/clk-pxa910.c delete mode 100644 include/linux/clk/mmp.h diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index cbcc2f8430a2..441bf83080a1 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -11,8 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o -obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o -obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o -obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o - obj-y += clk-of-pxa1928.o diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c deleted file mode 100644 index aabacfa10158..000000000000 --- a/drivers/clk/mmp/clk-mmp2.c +++ /dev/null @@ -1,454 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * mmp2 clock framework source file - * - * Copyright (C) 2012 Marvell - * Chao Xie - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk.h" - -#define APBC_RTC 0x0 -#define APBC_TWSI0 0x4 -#define APBC_TWSI1 0x8 -#define APBC_TWSI2 0xc -#define APBC_TWSI3 0x10 -#define APBC_TWSI4 0x7c -#define APBC_TWSI5 0x80 -#define APBC_KPC 0x18 -#define APBC_UART0 0x2c -#define APBC_UART1 0x30 -#define APBC_UART2 0x34 -#define APBC_UART3 0x88 -#define APBC_GPIO 0x38 -#define APBC_PWM0 0x3c -#define APBC_PWM1 0x40 -#define APBC_PWM2 0x44 -#define APBC_PWM3 0x48 -#define APBC_SSP0 0x50 -#define APBC_SSP1 0x54 -#define APBC_SSP2 0x58 -#define APBC_SSP3 0x5c -#define APMU_SDH0 0x54 -#define APMU_SDH1 0x58 -#define APMU_SDH2 0xe8 -#define APMU_SDH3 0xec -#define APMU_USB 0x5c -#define APMU_DISP0 0x4c -#define APMU_DISP1 0x110 -#define APMU_CCIC0 0x50 -#define APMU_CCIC1 0xf4 -#define MPMU_UART_PLL 0x14 - -static DEFINE_SPINLOCK(clk_lock); - -static struct mmp_clk_factor_masks uart_factor_masks = { - .factor = 2, - .num_mask = 0x1fff, - .den_mask = 0x1fff, - .num_shift = 16, - .den_shift = 0, -}; - -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ - {.num = 3521, .den = 689}, /*19.23MHZ */ -}; - -static const char *uart_parent[] = {"uart_pll", "vctcxo"}; -static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"}; -static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"}; -static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"}; -static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"}; - -void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys, - phys_addr_t apbc_phys) -{ - struct clk *clk; - struct clk *vctcxo; - void __iomem *mpmu_base; - void __iomem *apmu_base; - void __iomem *apbc_base; - - mpmu_base = ioremap(mpmu_phys, SZ_4K); - if (!mpmu_base) { - pr_err("error to ioremap MPMU base\n"); - return; - } - - apmu_base = ioremap(apmu_phys, SZ_4K); - if (!apmu_base) { - pr_err("error to ioremap APMU base\n"); - return; - } - - apbc_base = ioremap(apbc_phys, SZ_4K); - if (!apbc_base) { - pr_err("error to ioremap APBC base\n"); - return; - } - - clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); - clk_register_clkdev(clk, "clk32", NULL); - - vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); - clk_register_clkdev(vctcxo, "vctcxo", NULL); - - clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000); - clk_register_clkdev(clk, "pll1", NULL); - - clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000); - clk_register_clkdev(clk, "usb_pll", NULL); - - clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000); - clk_register_clkdev(clk, "pll2", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_2", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_4", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_8", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_16", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4", - CLK_SET_RATE_PARENT, 1, 5); - clk_register_clkdev(clk, "pll1_20", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1", - CLK_SET_RATE_PARENT, 1, 3); - clk_register_clkdev(clk, "pll1_3", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_6", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_12", NULL); - - clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll2_2", NULL); - - clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll2_4", NULL); - - clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll2_8", NULL); - - clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll2_16", NULL); - - clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2", - CLK_SET_RATE_PARENT, 1, 3); - clk_register_clkdev(clk, "pll2_3", NULL); - - clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll2_6", NULL); - - clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll2_12", NULL); - - clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "vctcxo_2", NULL); - - clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "vctcxo_4", NULL); - - clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0, - mpmu_base + MPMU_UART_PLL, - &uart_factor_masks, uart_factor_tbl, - ARRAY_SIZE(uart_factor_tbl), &clk_lock); - clk_set_rate(clk, 14745600); - clk_register_clkdev(clk, "uart_pll", NULL); - - clk = mmp_clk_register_apbc("twsi0", "vctcxo", - apbc_base + APBC_TWSI0, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); - - clk = mmp_clk_register_apbc("twsi1", "vctcxo", - apbc_base + APBC_TWSI1, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); - - clk = mmp_clk_register_apbc("twsi2", "vctcxo", - apbc_base + APBC_TWSI2, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2"); - - clk = mmp_clk_register_apbc("twsi3", "vctcxo", - apbc_base + APBC_TWSI3, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3"); - - clk = mmp_clk_register_apbc("twsi4", "vctcxo", - apbc_base + APBC_TWSI4, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4"); - - clk = mmp_clk_register_apbc("twsi5", "vctcxo", - apbc_base + APBC_TWSI5, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5"); - - clk = mmp_clk_register_apbc("gpio", "vctcxo", - apbc_base + APBC_GPIO, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp2-gpio"); - - clk = mmp_clk_register_apbc("kpc", "clk32", - apbc_base + APBC_KPC, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa27x-keypad"); - - clk = mmp_clk_register_apbc("rtc", "clk32", - apbc_base + APBC_RTC, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-rtc"); - - clk = mmp_clk_register_apbc("pwm0", "vctcxo", - apbc_base + APBC_PWM0, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp2-pwm.0"); - - clk = mmp_clk_register_apbc("pwm1", "vctcxo", - apbc_base + APBC_PWM1, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp2-pwm.1"); - - clk = mmp_clk_register_apbc("pwm2", "vctcxo", - apbc_base + APBC_PWM2, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp2-pwm.2"); - - clk = mmp_clk_register_apbc("pwm3", "vctcxo", - apbc_base + APBC_PWM3, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp2-pwm.3"); - - clk = clk_register_mux(NULL, "uart0_mux", uart_parent, - ARRAY_SIZE(uart_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); - clk_register_clkdev(clk, "uart_mux.0", NULL); - - clk = mmp_clk_register_apbc("uart0", "uart0_mux", - apbc_base + APBC_UART0, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); - - clk = clk_register_mux(NULL, "uart1_mux", uart_parent, - ARRAY_SIZE(uart_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); - clk_register_clkdev(clk, "uart_mux.1", NULL); - - clk = mmp_clk_register_apbc("uart1", "uart1_mux", - apbc_base + APBC_UART1, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); - - clk = clk_register_mux(NULL, "uart2_mux", uart_parent, - ARRAY_SIZE(uart_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); - clk_register_clkdev(clk, "uart_mux.2", NULL); - - clk = mmp_clk_register_apbc("uart2", "uart2_mux", - apbc_base + APBC_UART2, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); - - clk = clk_register_mux(NULL, "uart3_mux", uart_parent, - ARRAY_SIZE(uart_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); - clk_register_clkdev(clk, "uart_mux.3", NULL); - - clk = mmp_clk_register_apbc("uart3", "uart3_mux", - apbc_base + APBC_UART3, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-uart.3"); - - clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, - ARRAY_SIZE(ssp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "uart_mux.0", NULL); - - clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", - apbc_base + APBC_SSP0, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.0"); - - clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, - ARRAY_SIZE(ssp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "ssp_mux.1", NULL); - - clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", - apbc_base + APBC_SSP1, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.1"); - - clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, - ARRAY_SIZE(ssp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "ssp_mux.2", NULL); - - clk = mmp_clk_register_apbc("ssp2", "ssp2_mux", - apbc_base + APBC_SSP2, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.2"); - - clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, - ARRAY_SIZE(ssp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "ssp_mux.3", NULL); - - clk = mmp_clk_register_apbc("ssp3", "ssp3_mux", - apbc_base + APBC_SSP3, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.3"); - - clk = clk_register_mux(NULL, "sdh_mux", sdh_parent, - ARRAY_SIZE(sdh_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock); - clk_register_clkdev(clk, "sdh_mux", NULL); - - clk = clk_register_divider(NULL, "sdh_div", "sdh_mux", - CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, - 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); - clk_register_clkdev(clk, "sdh_div", NULL); - - clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0, - 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "sdhci-pxav3.0"); - - clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1, - 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "sdhci-pxav3.1"); - - clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2, - 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "sdhci-pxav3.2"); - - clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3, - 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "sdhci-pxav3.3"); - - clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, - 0x9, &clk_lock); - clk_register_clkdev(clk, "usb_clk", NULL); - - clk = clk_register_mux(NULL, "disp0_mux", disp_parent, - ARRAY_SIZE(disp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock); - clk_register_clkdev(clk, "disp_mux.0", NULL); - - clk = clk_register_divider(NULL, "disp0_div", "disp0_mux", - CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0, - 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); - clk_register_clkdev(clk, "disp_div.0", NULL); - - clk = mmp_clk_register_apmu("disp0", "disp0_div", - apmu_base + APMU_DISP0, 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-disp.0"); - - clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0, - apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock); - clk_register_clkdev(clk, "disp_sphy_div.0", NULL); - - clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div", - apmu_base + APMU_DISP0, 0x1024, &clk_lock); - clk_register_clkdev(clk, "disp_sphy.0", NULL); - - clk = clk_register_mux(NULL, "disp1_mux", disp_parent, - ARRAY_SIZE(disp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock); - clk_register_clkdev(clk, "disp_mux.1", NULL); - - clk = clk_register_divider(NULL, "disp1_div", "disp1_mux", - CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1, - 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); - clk_register_clkdev(clk, "disp_div.1", NULL); - - clk = mmp_clk_register_apmu("disp1", "disp1_div", - apmu_base + APMU_DISP1, 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-disp.1"); - - clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo", - apmu_base + APMU_CCIC0, 0x1800, &clk_lock); - clk_register_clkdev(clk, "ccic_arbiter", NULL); - - clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, - ARRAY_SIZE(ccic_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); - clk_register_clkdev(clk, "ccic_mux.0", NULL); - - clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux", - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, - 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); - clk_register_clkdev(clk, "ccic_div.0", NULL); - - clk = mmp_clk_register_apmu("ccic0", "ccic0_div", - apmu_base + APMU_CCIC0, 0x1b, &clk_lock); - clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); - - clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div", - apmu_base + APMU_CCIC0, 0x24, &clk_lock); - clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); - - clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div", - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, - 10, 5, 0, &clk_lock); - clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0"); - - clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", - apmu_base + APMU_CCIC0, 0x300, &clk_lock); - clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); - - clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent, - ARRAY_SIZE(ccic_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock); - clk_register_clkdev(clk, "ccic_mux.1", NULL); - - clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux", - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, - 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); - clk_register_clkdev(clk, "ccic_div.1", NULL); - - clk = mmp_clk_register_apmu("ccic1", "ccic1_div", - apmu_base + APMU_CCIC1, 0x1b, &clk_lock); - clk_register_clkdev(clk, "fnclk", "mmp-ccic.1"); - - clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div", - apmu_base + APMU_CCIC1, 0x24, &clk_lock); - clk_register_clkdev(clk, "phyclk", "mmp-ccic.1"); - - clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div", - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, - 10, 5, 0, &clk_lock); - clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1"); - - clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div", - apmu_base + APMU_CCIC1, 0x300, &clk_lock); - clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1"); -} diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c deleted file mode 100644 index 8a9b8fb3a465..000000000000 --- a/drivers/clk/mmp/clk-pxa168.c +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * pxa168 clock framework source file - * - * Copyright (C) 2012 Marvell - * Chao Xie - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk.h" - -#define APBC_RTC 0x28 -#define APBC_TWSI0 0x2c -#define APBC_KPC 0x30 -#define APBC_UART0 0x0 -#define APBC_UART1 0x4 -#define APBC_GPIO 0x8 -#define APBC_PWM0 0xc -#define APBC_PWM1 0x10 -#define APBC_PWM2 0x14 -#define APBC_PWM3 0x18 -#define APBC_SSP0 0x81c -#define APBC_SSP1 0x820 -#define APBC_SSP2 0x84c -#define APBC_SSP3 0x858 -#define APBC_SSP4 0x85c -#define APBC_TWSI1 0x6c -#define APBC_UART2 0x70 -#define APMU_SDH0 0x54 -#define APMU_SDH1 0x58 -#define APMU_USB 0x5c -#define APMU_DISP0 0x4c -#define APMU_CCIC0 0x50 -#define APMU_DFC 0x60 -#define MPMU_UART_PLL 0x14 - -static DEFINE_SPINLOCK(clk_lock); - -static struct mmp_clk_factor_masks uart_factor_masks = { - .factor = 2, - .num_mask = 0x1fff, - .den_mask = 0x1fff, - .num_shift = 16, - .den_shift = 0, -}; - -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ -}; - -static const char *uart_parent[] = {"pll1_3_16", "uart_pll"}; -static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; -static const char *sdh_parent[] = {"pll1_12", "pll1_13"}; -static const char *disp_parent[] = {"pll1_2", "pll1_12"}; -static const char *ccic_parent[] = {"pll1_2", "pll1_12"}; -static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; - -void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys, - phys_addr_t apbc_phys) -{ - struct clk *clk; - struct clk *uart_pll; - void __iomem *mpmu_base; - void __iomem *apmu_base; - void __iomem *apbc_base; - - mpmu_base = ioremap(mpmu_phys, SZ_4K); - if (!mpmu_base) { - pr_err("error to ioremap MPMU base\n"); - return; - } - - apmu_base = ioremap(apmu_phys, SZ_4K); - if (!apmu_base) { - pr_err("error to ioremap APMU base\n"); - return; - } - - apbc_base = ioremap(apbc_phys, SZ_4K); - if (!apbc_base) { - pr_err("error to ioremap APBC base\n"); - return; - } - - clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); - clk_register_clkdev(clk, "clk32", NULL); - - clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); - clk_register_clkdev(clk, "vctcxo", NULL); - - clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); - clk_register_clkdev(clk, "pll1", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_2", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_4", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_8", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_16", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", - CLK_SET_RATE_PARENT, 1, 3); - clk_register_clkdev(clk, "pll1_6", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_12", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_24", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_48", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_96", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", - CLK_SET_RATE_PARENT, 1, 13); - clk_register_clkdev(clk, "pll1_13", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", - CLK_SET_RATE_PARENT, 2, 3); - clk_register_clkdev(clk, "pll1_13_1_5", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", - CLK_SET_RATE_PARENT, 2, 3); - clk_register_clkdev(clk, "pll1_2_1_5", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", - CLK_SET_RATE_PARENT, 3, 16); - clk_register_clkdev(clk, "pll1_3_16", NULL); - - uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0, - mpmu_base + MPMU_UART_PLL, - &uart_factor_masks, uart_factor_tbl, - ARRAY_SIZE(uart_factor_tbl), &clk_lock); - clk_set_rate(uart_pll, 14745600); - clk_register_clkdev(uart_pll, "uart_pll", NULL); - - clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", - apbc_base + APBC_TWSI0, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); - - clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", - apbc_base + APBC_TWSI1, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); - - clk = mmp_clk_register_apbc("gpio", "vctcxo", - apbc_base + APBC_GPIO, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-gpio"); - - clk = mmp_clk_register_apbc("kpc", "clk32", - apbc_base + APBC_KPC, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa27x-keypad"); - - clk = mmp_clk_register_apbc("rtc", "clk32", - apbc_base + APBC_RTC, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "sa1100-rtc"); - - clk = mmp_clk_register_apbc("pwm0", "pll1_48", - apbc_base + APBC_PWM0, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa168-pwm.0"); - - clk = mmp_clk_register_apbc("pwm1", "pll1_48", - apbc_base + APBC_PWM1, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa168-pwm.1"); - - clk = mmp_clk_register_apbc("pwm2", "pll1_48", - apbc_base + APBC_PWM2, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa168-pwm.2"); - - clk = mmp_clk_register_apbc("pwm3", "pll1_48", - apbc_base + APBC_PWM3, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa168-pwm.3"); - - clk = clk_register_mux(NULL, "uart0_mux", uart_parent, - ARRAY_SIZE(uart_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); - clk_register_clkdev(clk, "uart_mux.0", NULL); - - clk = mmp_clk_register_apbc("uart0", "uart0_mux", - apbc_base + APBC_UART0, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); - - clk = clk_register_mux(NULL, "uart1_mux", uart_parent, - ARRAY_SIZE(uart_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); - clk_register_clkdev(clk, "uart_mux.1", NULL); - - clk = mmp_clk_register_apbc("uart1", "uart1_mux", - apbc_base + APBC_UART1, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); - - clk = clk_register_mux(NULL, "uart2_mux", uart_parent, - ARRAY_SIZE(uart_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); - clk_register_clkdev(clk, "uart_mux.2", NULL); - - clk = mmp_clk_register_apbc("uart2", "uart2_mux", - apbc_base + APBC_UART2, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); - - clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, - ARRAY_SIZE(ssp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "uart_mux.0", NULL); - - clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, - 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.0"); - - clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, - ARRAY_SIZE(ssp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "ssp_mux.1", NULL); - - clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, - 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.1"); - - clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, - ARRAY_SIZE(ssp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "ssp_mux.2", NULL); - - clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, - 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.2"); - - clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, - ARRAY_SIZE(ssp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "ssp_mux.3", NULL); - - clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3, - 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.3"); - - clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent, - ARRAY_SIZE(ssp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "ssp_mux.4", NULL); - - clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4, - 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.4"); - - clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, - 0x19b, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); - - clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, - ARRAY_SIZE(sdh_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); - clk_register_clkdev(clk, "sdh0_mux", NULL); - - clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0, - 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); - - clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, - ARRAY_SIZE(sdh_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); - clk_register_clkdev(clk, "sdh1_mux", NULL); - - clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1, - 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); - - clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, - 0x9, &clk_lock); - clk_register_clkdev(clk, "usb_clk", NULL); - - clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, - 0x12, &clk_lock); - clk_register_clkdev(clk, "sph_clk", NULL); - - clk = clk_register_mux(NULL, "disp0_mux", disp_parent, - ARRAY_SIZE(disp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); - clk_register_clkdev(clk, "disp_mux.0", NULL); - - clk = mmp_clk_register_apmu("disp0", "disp0_mux", - apmu_base + APMU_DISP0, 0x1b, &clk_lock); - clk_register_clkdev(clk, "fnclk", "mmp-disp.0"); - - clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux", - apmu_base + APMU_DISP0, 0x24, &clk_lock); - clk_register_clkdev(clk, "hclk", "mmp-disp.0"); - - clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, - ARRAY_SIZE(ccic_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); - clk_register_clkdev(clk, "ccic_mux.0", NULL); - - clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", - apmu_base + APMU_CCIC0, 0x1b, &clk_lock); - clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); - - clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, - ARRAY_SIZE(ccic_phy_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); - clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); - - clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", - apmu_base + APMU_CCIC0, 0x24, &clk_lock); - clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); - - clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, - 10, 5, 0, &clk_lock); - clk_register_clkdev(clk, "sphyclk_div", NULL); - - clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", - apmu_base + APMU_CCIC0, 0x300, &clk_lock); - clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); -} diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c deleted file mode 100644 index 9fcd76316d7e..000000000000 --- a/drivers/clk/mmp/clk-pxa910.c +++ /dev/null @@ -1,325 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * pxa910 clock framework source file - * - * Copyright (C) 2012 Marvell - * Chao Xie - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk.h" - -#define APBC_RTC 0x28 -#define APBC_TWSI0 0x2c -#define APBC_KPC 0x18 -#define APBC_UART0 0x0 -#define APBC_UART1 0x4 -#define APBC_GPIO 0x8 -#define APBC_PWM0 0xc -#define APBC_PWM1 0x10 -#define APBC_PWM2 0x14 -#define APBC_PWM3 0x18 -#define APBC_SSP0 0x1c -#define APBC_SSP1 0x20 -#define APBC_SSP2 0x4c -#define APBCP_TWSI1 0x28 -#define APBCP_UART2 0x1c -#define APMU_SDH0 0x54 -#define APMU_SDH1 0x58 -#define APMU_USB 0x5c -#define APMU_DISP0 0x4c -#define APMU_CCIC0 0x50 -#define APMU_DFC 0x60 -#define MPMU_UART_PLL 0x14 - -static DEFINE_SPINLOCK(clk_lock); - -static struct mmp_clk_factor_masks uart_factor_masks = { - .factor = 2, - .num_mask = 0x1fff, - .den_mask = 0x1fff, - .num_shift = 16, - .den_shift = 0, -}; - -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ -}; - -static const char *uart_parent[] = {"pll1_3_16", "uart_pll"}; -static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; -static const char *sdh_parent[] = {"pll1_12", "pll1_13"}; -static const char *disp_parent[] = {"pll1_2", "pll1_12"}; -static const char *ccic_parent[] = {"pll1_2", "pll1_12"}; -static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; - -void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys, - phys_addr_t apbc_phys, phys_addr_t apbcp_phys) -{ - struct clk *clk; - struct clk *uart_pll; - void __iomem *mpmu_base; - void __iomem *apmu_base; - void __iomem *apbcp_base; - void __iomem *apbc_base; - - mpmu_base = ioremap(mpmu_phys, SZ_4K); - if (!mpmu_base) { - pr_err("error to ioremap MPMU base\n"); - return; - } - - apmu_base = ioremap(apmu_phys, SZ_4K); - if (!apmu_base) { - pr_err("error to ioremap APMU base\n"); - return; - } - - apbcp_base = ioremap(apbcp_phys, SZ_4K); - if (!apbcp_base) { - pr_err("error to ioremap APBC extension base\n"); - return; - } - - apbc_base = ioremap(apbc_phys, SZ_4K); - if (!apbc_base) { - pr_err("error to ioremap APBC base\n"); - return; - } - - clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); - clk_register_clkdev(clk, "clk32", NULL); - - clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); - clk_register_clkdev(clk, "vctcxo", NULL); - - clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); - clk_register_clkdev(clk, "pll1", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_2", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_4", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_8", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_16", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", - CLK_SET_RATE_PARENT, 1, 3); - clk_register_clkdev(clk, "pll1_6", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_12", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_24", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_48", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", - CLK_SET_RATE_PARENT, 1, 2); - clk_register_clkdev(clk, "pll1_96", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", - CLK_SET_RATE_PARENT, 1, 13); - clk_register_clkdev(clk, "pll1_13", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", - CLK_SET_RATE_PARENT, 2, 3); - clk_register_clkdev(clk, "pll1_13_1_5", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", - CLK_SET_RATE_PARENT, 2, 3); - clk_register_clkdev(clk, "pll1_2_1_5", NULL); - - clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", - CLK_SET_RATE_PARENT, 3, 16); - clk_register_clkdev(clk, "pll1_3_16", NULL); - - uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0, - mpmu_base + MPMU_UART_PLL, - &uart_factor_masks, uart_factor_tbl, - ARRAY_SIZE(uart_factor_tbl), &clk_lock); - clk_set_rate(uart_pll, 14745600); - clk_register_clkdev(uart_pll, "uart_pll", NULL); - - clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", - apbc_base + APBC_TWSI0, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); - - clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", - apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); - - clk = mmp_clk_register_apbc("gpio", "vctcxo", - apbc_base + APBC_GPIO, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-gpio"); - - clk = mmp_clk_register_apbc("kpc", "clk32", - apbc_base + APBC_KPC, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa27x-keypad"); - - clk = mmp_clk_register_apbc("rtc", "clk32", - apbc_base + APBC_RTC, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "sa1100-rtc"); - - clk = mmp_clk_register_apbc("pwm0", "pll1_48", - apbc_base + APBC_PWM0, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa910-pwm.0"); - - clk = mmp_clk_register_apbc("pwm1", "pll1_48", - apbc_base + APBC_PWM1, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa910-pwm.1"); - - clk = mmp_clk_register_apbc("pwm2", "pll1_48", - apbc_base + APBC_PWM2, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa910-pwm.2"); - - clk = mmp_clk_register_apbc("pwm3", "pll1_48", - apbc_base + APBC_PWM3, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa910-pwm.3"); - - clk = clk_register_mux(NULL, "uart0_mux", uart_parent, - ARRAY_SIZE(uart_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); - clk_register_clkdev(clk, "uart_mux.0", NULL); - - clk = mmp_clk_register_apbc("uart0", "uart0_mux", - apbc_base + APBC_UART0, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); - - clk = clk_register_mux(NULL, "uart1_mux", uart_parent, - ARRAY_SIZE(uart_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); - clk_register_clkdev(clk, "uart_mux.1", NULL); - - clk = mmp_clk_register_apbc("uart1", "uart1_mux", - apbc_base + APBC_UART1, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); - - clk = clk_register_mux(NULL, "uart2_mux", uart_parent, - ARRAY_SIZE(uart_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); - clk_register_clkdev(clk, "uart_mux.2", NULL); - - clk = mmp_clk_register_apbc("uart2", "uart2_mux", - apbcp_base + APBCP_UART2, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); - - clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, - ARRAY_SIZE(ssp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "uart_mux.0", NULL); - - clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", - apbc_base + APBC_SSP0, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.0"); - - clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, - ARRAY_SIZE(ssp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "ssp_mux.1", NULL); - - clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", - apbc_base + APBC_SSP1, 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.1"); - - clk = mmp_clk_register_apmu("dfc", "pll1_4", - apmu_base + APMU_DFC, 0x19b, &clk_lock); - clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); - - clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, - ARRAY_SIZE(sdh_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); - clk_register_clkdev(clk, "sdh0_mux", NULL); - - clk = mmp_clk_register_apmu("sdh0", "sdh_mux", - apmu_base + APMU_SDH0, 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); - - clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, - ARRAY_SIZE(sdh_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); - clk_register_clkdev(clk, "sdh1_mux", NULL); - - clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", - apmu_base + APMU_SDH1, 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); - - clk = mmp_clk_register_apmu("usb", "usb_pll", - apmu_base + APMU_USB, 0x9, &clk_lock); - clk_register_clkdev(clk, "usb_clk", NULL); - - clk = mmp_clk_register_apmu("sph", "usb_pll", - apmu_base + APMU_USB, 0x12, &clk_lock); - clk_register_clkdev(clk, "sph_clk", NULL); - - clk = clk_register_mux(NULL, "disp0_mux", disp_parent, - ARRAY_SIZE(disp_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); - clk_register_clkdev(clk, "disp_mux.0", NULL); - - clk = mmp_clk_register_apmu("disp0", "disp0_mux", - apmu_base + APMU_DISP0, 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-disp.0"); - - clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, - ARRAY_SIZE(ccic_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); - clk_register_clkdev(clk, "ccic_mux.0", NULL); - - clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", - apmu_base + APMU_CCIC0, 0x1b, &clk_lock); - clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); - - clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, - ARRAY_SIZE(ccic_phy_parent), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); - clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); - - clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", - apmu_base + APMU_CCIC0, 0x24, &clk_lock); - clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); - - clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, - 10, 5, 0, &clk_lock); - clk_register_clkdev(clk, "sphyclk_div", NULL); - - clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", - apmu_base + APMU_CCIC0, 0x300, &clk_lock); - clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); -} diff --git a/include/linux/clk/mmp.h b/include/linux/clk/mmp.h deleted file mode 100644 index 445130460380..000000000000 --- a/include/linux/clk/mmp.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __CLK_MMP_H -#define __CLK_MMP_H - -#include - -extern void pxa168_clk_init(phys_addr_t mpmu_phys, - phys_addr_t apmu_phys, - phys_addr_t apbc_phys); -extern void pxa910_clk_init(phys_addr_t mpmu_phys, - phys_addr_t apmu_phys, - phys_addr_t apbc_phys, - phys_addr_t apbcp_phys); -extern void mmp2_clk_init(phys_addr_t mpmu_phys, - phys_addr_t apmu_phys, - phys_addr_t apbc_phys); - -#endif From 46c13513a4af9e5ca8b286ab8f3afecb1404282a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= Date: Sat, 12 Aug 2023 12:02:56 +0200 Subject: [PATCH 31/37] clk: mmp2: Move number of clocks to driver source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-1-f9271bd7eaa5@skole.hr Acked-by: Conor Dooley Signed-off-by: Stephen Boyd --- drivers/clk/mmp/clk-audio.c | 6 ++++-- drivers/clk/mmp/clk-of-mmp2.c | 4 +++- include/dt-bindings/clock/marvell,mmp2-audio.h | 1 - include/dt-bindings/clock/marvell,mmp2.h | 1 - 4 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/mmp/clk-audio.c b/drivers/clk/mmp/clk-audio.c index 6fb1aa9487b5..ae521aaf8cdc 100644 --- a/drivers/clk/mmp/clk-audio.c +++ b/drivers/clk/mmp/clk-audio.c @@ -55,6 +55,8 @@ #define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK (0x7ff << 0) #define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(x) ((x) << 0) +#define CLK_AUDIO_NR_CLKS 3 + struct mmp2_audio_clk { void __iomem *mmio_base; @@ -336,7 +338,7 @@ static int register_clocks(struct mmp2_audio_clk *priv, struct device *dev) priv->clk_data.hws[MMP2_CLK_AUDIO_SYSCLK] = &priv->sysclk_gate.hw; priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA0] = &priv->sspa0_gate.hw; priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA1] = &priv->sspa1_gate.hw; - priv->clk_data.num = MMP2_CLK_AUDIO_NR_CLKS; + priv->clk_data.num = CLK_AUDIO_NR_CLKS; return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, &priv->clk_data); @@ -349,7 +351,7 @@ static int mmp2_audio_clk_probe(struct platform_device *pdev) priv = devm_kzalloc(&pdev->dev, struct_size(priv, clk_data.hws, - MMP2_CLK_AUDIO_NR_CLKS), + CLK_AUDIO_NR_CLKS), GFP_KERNEL); if (!priv) return -ENOMEM; diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index bcf60f43aa13..eaad36ee323d 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -78,6 +78,8 @@ #define MPMU_PLL_DIFF_CTRL 0x68 #define MPMU_PLL2_CTRL1 0x414 +#define NR_CLKS 200 + enum mmp2_clk_model { CLK_MODEL_MMP2, CLK_MODEL_MMP3, @@ -543,7 +545,7 @@ static void __init mmp2_clk_init(struct device_node *np) mmp2_pm_domain_init(np, pxa_unit); - mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS); + mmp_clk_init(np, &pxa_unit->unit, NR_CLKS); mmp2_main_clk_init(pxa_unit); diff --git a/include/dt-bindings/clock/marvell,mmp2-audio.h b/include/dt-bindings/clock/marvell,mmp2-audio.h index 20664776f497..9653e04dedc3 100644 --- a/include/dt-bindings/clock/marvell,mmp2-audio.h +++ b/include/dt-bindings/clock/marvell,mmp2-audio.h @@ -6,5 +6,4 @@ #define MMP2_CLK_AUDIO_SSPA0 1 #define MMP2_CLK_AUDIO_SSPA1 2 -#define MMP2_CLK_AUDIO_NR_CLKS 3 #endif diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h index f0819d66b230..88c2d716476f 100644 --- a/include/dt-bindings/clock/marvell,mmp2.h +++ b/include/dt-bindings/clock/marvell,mmp2.h @@ -91,5 +91,4 @@ #define MMP3_CLK_SDH4 126 #define MMP2_CLK_AUDIO 127 -#define MMP2_NR_CLKS 200 #endif From 51fa6aa5c2c2b85b6ddaab267cf03ef30417ef67 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= Date: Sat, 12 Aug 2023 12:02:57 +0200 Subject: [PATCH 32/37] clk: pxa168: Move number of clocks to driver source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-2-f9271bd7eaa5@skole.hr Acked-by: Conor Dooley Signed-off-by: Stephen Boyd --- drivers/clk/mmp/clk-of-pxa168.c | 4 +++- include/dt-bindings/clock/marvell,pxa168.h | 1 - 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c index 130d1a723879..fb0df64cf053 100644 --- a/drivers/clk/mmp/clk-of-pxa168.c +++ b/drivers/clk/mmp/clk-of-pxa168.c @@ -62,6 +62,8 @@ #define APMU_EPD 0x104 #define MPMU_UART_PLL 0x14 +#define NR_CLKS 200 + struct pxa168_clk_unit { struct mmp_clk_unit unit; void __iomem *mpmu_base; @@ -321,7 +323,7 @@ static void __init pxa168_clk_init(struct device_node *np) return; } - mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS); + mmp_clk_init(np, &pxa_unit->unit, NR_CLKS); pxa168_pll_init(pxa_unit); diff --git a/include/dt-bindings/clock/marvell,pxa168.h b/include/dt-bindings/clock/marvell,pxa168.h index c92d969ae941..d1bb59187e1d 100644 --- a/include/dt-bindings/clock/marvell,pxa168.h +++ b/include/dt-bindings/clock/marvell,pxa168.h @@ -63,5 +63,4 @@ #define PXA168_CLK_SDH01_AXI 111 #define PXA168_CLK_SDH23_AXI 112 -#define PXA168_NR_CLKS 200 #endif From 87f06247e031dc7bbc864efecb6feb77d452813f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= Date: Sat, 12 Aug 2023 12:02:58 +0200 Subject: [PATCH 33/37] clk: pxa1928: Move number of clocks to driver source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-3-f9271bd7eaa5@skole.hr Acked-by: Conor Dooley Signed-off-by: Stephen Boyd --- drivers/clk/mmp/clk-of-pxa1928.c | 7 +++++-- include/dt-bindings/clock/marvell,pxa1928.h | 3 --- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/mmp/clk-of-pxa1928.c b/drivers/clk/mmp/clk-of-pxa1928.c index 2508a0d795f8..9def4b5f10e9 100644 --- a/drivers/clk/mmp/clk-of-pxa1928.c +++ b/drivers/clk/mmp/clk-of-pxa1928.c @@ -22,6 +22,9 @@ #define MPMU_UART_PLL 0x14 +#define APBC_NR_CLKS 48 +#define APMU_NR_CLKS 96 + struct pxa1928_clk_unit { struct mmp_clk_unit unit; void __iomem *mpmu_base; @@ -235,7 +238,7 @@ static void __init pxa1928_apmu_clk_init(struct device_node *np) return; } - mmp_clk_init(np, &pxa_unit->unit, PXA1928_APMU_NR_CLKS); + mmp_clk_init(np, &pxa_unit->unit, APMU_NR_CLKS); pxa1928_axi_periph_clk_init(pxa_unit); } @@ -256,7 +259,7 @@ static void __init pxa1928_apbc_clk_init(struct device_node *np) return; } - mmp_clk_init(np, &pxa_unit->unit, PXA1928_APBC_NR_CLKS); + mmp_clk_init(np, &pxa_unit->unit, APBC_NR_CLKS); pxa1928_apb_periph_clk_init(pxa_unit); pxa1928_clk_reset_init(np, pxa_unit); diff --git a/include/dt-bindings/clock/marvell,pxa1928.h b/include/dt-bindings/clock/marvell,pxa1928.h index 5dca4820297f..0c708d3d3314 100644 --- a/include/dt-bindings/clock/marvell,pxa1928.h +++ b/include/dt-bindings/clock/marvell,pxa1928.h @@ -36,7 +36,6 @@ #define PXA1928_CLK_THSENS_CPU 0x26 #define PXA1928_CLK_THSENS_VPU 0x27 #define PXA1928_CLK_THSENS_GC 0x28 -#define PXA1928_APBC_NR_CLKS 0x30 /* axi peripherals */ @@ -53,6 +52,4 @@ #define PXA1928_CLK_GC3D 0x5d #define PXA1928_CLK_GC2D 0x5f -#define PXA1928_APMU_NR_CLKS 0x60 - #endif From 3b99cd274e43b89c89a4072c602b1df6000eb1f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= Date: Sat, 12 Aug 2023 12:02:59 +0200 Subject: [PATCH 34/37] clk: pxa910: Move number of clocks to driver source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-4-f9271bd7eaa5@skole.hr Acked-by: Conor Dooley Signed-off-by: Stephen Boyd --- drivers/clk/mmp/clk-of-pxa910.c | 4 +++- include/dt-bindings/clock/marvell,pxa910.h | 1 - 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c index 4d15bac987eb..7a38c424782e 100644 --- a/drivers/clk/mmp/clk-of-pxa910.c +++ b/drivers/clk/mmp/clk-of-pxa910.c @@ -44,6 +44,8 @@ #define APMU_DFC 0x60 #define MPMU_UART_PLL 0x14 +#define NR_CLKS 200 + struct pxa910_clk_unit { struct mmp_clk_unit unit; void __iomem *mpmu_base; @@ -296,7 +298,7 @@ static void __init pxa910_clk_init(struct device_node *np) goto unmap_apbc_region; } - mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS); + mmp_clk_init(np, &pxa_unit->unit, NR_CLKS); pxa910_pll_init(pxa_unit); diff --git a/include/dt-bindings/clock/marvell,pxa910.h b/include/dt-bindings/clock/marvell,pxa910.h index c9018ab354d0..6caa231de0c1 100644 --- a/include/dt-bindings/clock/marvell,pxa910.h +++ b/include/dt-bindings/clock/marvell,pxa910.h @@ -55,5 +55,4 @@ #define PXA910_CLK_CCIC0_PHY 108 #define PXA910_CLK_CCIC0_SPHY 109 -#define PXA910_NR_CLKS 200 #endif From f6d6c11f417a50caca9d30d63f0f85c311c09869 Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Wed, 2 Aug 2023 08:40:58 +0200 Subject: [PATCH 35/37] clk: lmk04832: Set missing parent_names for output clocks lmk04832_register_clkout forgot to fill in the parent_names, resulting in the error message "Must specify parents if num_parents > 0". Signed-off-by: Mike Looijmans Link: https://lore.kernel.org/r/20230802064100.15793-1-mike.looijmans@topic.nl Reviewed-by: Liam Beguin Signed-off-by: Stephen Boyd --- drivers/clk/clk-lmk04832.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c index e22ac93e0c2f..188085e7a30b 100644 --- a/drivers/clk/clk-lmk04832.c +++ b/drivers/clk/clk-lmk04832.c @@ -1297,6 +1297,7 @@ static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num) sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1); init.name = dclk_name; parent_names[0] = clk_hw_get_name(&lmk->vco); + init.parent_names = parent_names; init.ops = &lmk04832_dclk_ops; init.flags = CLK_SET_RATE_PARENT; init.num_parents = 1; From e63227c83cff755c4d3b326d317d2e88451a637f Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Wed, 2 Aug 2023 08:40:59 +0200 Subject: [PATCH 36/37] clk: lmk04832: Don't disable vco clock on probe fail The probe() method never calls clk_prepare_enable(), so it should not call clk_disable_unprepare() for the vco.clk in the error path. Fixes a "lmk-vco already disabled" BUG when probe fails. Signed-off-by: Mike Looijmans Link: https://lore.kernel.org/r/20230802064100.15793-2-mike.looijmans@topic.nl Reviewed-by: Liam Beguin Signed-off-by: Stephen Boyd --- drivers/clk/clk-lmk04832.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c index 188085e7a30b..dd1f0c59ee71 100644 --- a/drivers/clk/clk-lmk04832.c +++ b/drivers/clk/clk-lmk04832.c @@ -1505,21 +1505,21 @@ static int lmk04832_probe(struct spi_device *spi) ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate); if (ret) { dev_err(lmk->dev, "failed to set VCO rate\n"); - goto err_disable_vco; + goto err_disable_oscin; } } ret = lmk04832_register_sclk(lmk); if (ret) { dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n"); - goto err_disable_vco; + goto err_disable_oscin; } for (i = 0; i < info->num_channels; i++) { ret = lmk04832_register_clkout(lmk, i); if (ret) { dev_err(lmk->dev, "failed to register clk %d\n", i); - goto err_disable_vco; + goto err_disable_oscin; } } @@ -1528,16 +1528,13 @@ static int lmk04832_probe(struct spi_device *spi) lmk->clk_data); if (ret) { dev_err(lmk->dev, "failed to add provider (%d)\n", ret); - goto err_disable_vco; + goto err_disable_oscin; } spi_set_drvdata(spi, lmk); return 0; -err_disable_vco: - clk_disable_unprepare(lmk->vco.clk); - err_disable_oscin: clk_disable_unprepare(lmk->oscin); From 6aa8dc690d99f7aa7fc41f5606c7ee9ad481ad0b Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Wed, 2 Aug 2023 08:41:00 +0200 Subject: [PATCH 37/37] clk: lmk04832: Support using PLL1_LD as SPI readback pin The PLL1_PD pin (a.k.a. STATUS_LD1) can be used as SPI readback pin. Make this possible. Signed-off-by: Mike Looijmans Link: https://lore.kernel.org/r/20230802064100.15793-3-mike.looijmans@topic.nl Reviewed-by: Liam Beguin Signed-off-by: Stephen Boyd --- drivers/clk/clk-lmk04832.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c index dd1f0c59ee71..99b271c1278a 100644 --- a/drivers/clk/clk-lmk04832.c +++ b/drivers/clk/clk-lmk04832.c @@ -134,6 +134,11 @@ /* 0x14b - 0x152 Holdover */ /* 0x153 - 0x15f PLL1 Configuration */ +#define LMK04832_REG_PLL1_LD 0x15f +#define LMK04832_BIT_PLL1_LD_MUX GENMASK(7, 3) +#define LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK 0x07 +#define LMK04832_BIT_PLL1_LD_TYPE GENMASK(2, 0) +#define LMK04832_VAL_PLL1_LD_TYPE_OUT_PP 0x03 /* 0x160 - 0x16e PLL2 Configuration */ #define LMK04832_REG_PLL2_R_MSB 0x160 @@ -206,6 +211,7 @@ enum lmk04832_rdbk_type { RDBK_CLKIN_SEL0, RDBK_CLKIN_SEL1, RDBK_RESET, + RDBK_PLL1_LD, }; struct lmk_dclk { @@ -1346,6 +1352,10 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin) { int reg; int ret; + int val = FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX, + LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) | + FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE, + LMK04832_VAL_CLKIN_SEL_TYPE_OUT); dev_info(lmk->dev, "setting up 4-wire mode\n"); ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W, @@ -1363,15 +1373,18 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin) case RDBK_RESET: reg = LMK04832_REG_CLKIN_RST; break; + case RDBK_PLL1_LD: + reg = LMK04832_REG_PLL1_LD; + val = FIELD_PREP(LMK04832_BIT_PLL1_LD_MUX, + LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK) | + FIELD_PREP(LMK04832_BIT_PLL1_LD_TYPE, + LMK04832_VAL_PLL1_LD_TYPE_OUT_PP); + break; default: return -EINVAL; } - return regmap_write(lmk->regmap, reg, - FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX, - LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) | - FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE, - LMK04832_VAL_CLKIN_SEL_TYPE_OUT)); + return regmap_write(lmk->regmap, reg, val); } static int lmk04832_probe(struct spi_device *spi)