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drm/i915: Clean up cursor registers
Use REG_BIT() & co. to polish the cursor plane registers. v2: deal with gvt Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-12-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
This commit is contained in:
parent
f6bb74e077
commit
348abd4cf3
5 changed files with 56 additions and 50 deletions
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@ -51,16 +51,16 @@ static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
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u32 pos = 0;
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if (x < 0) {
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pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
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pos |= CURSOR_POS_X_SIGN;
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x = -x;
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}
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pos |= x << CURSOR_X_SHIFT;
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pos |= CURSOR_POS_X(x);
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if (y < 0) {
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pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
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pos |= CURSOR_POS_Y_SIGN;
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y = -y;
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}
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pos |= y << CURSOR_Y_SHIFT;
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pos |= CURSOR_POS_Y(y);
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return pos;
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}
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@ -180,7 +180,7 @@ static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
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u32 cntl = 0;
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if (crtc_state->gamma_enable)
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cntl |= CURSOR_GAMMA_ENABLE;
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cntl |= CURSOR_PIPE_GAMMA_ENABLE;
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return cntl;
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}
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@ -264,7 +264,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
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cntl = plane_state->ctl |
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i845_cursor_ctl_crtc(crtc_state);
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size = (height << 12) | width;
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size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
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base = intel_cursor_base(plane_state);
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pos = intel_cursor_position(plane_state);
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@ -280,7 +280,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
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plane->cursor.cntl != cntl) {
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intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
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intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
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intel_de_write_fw(dev_priv, CURSIZE, size);
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intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
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intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
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intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
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@ -340,13 +340,13 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
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return cntl;
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if (crtc_state->gamma_enable)
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cntl = MCURSOR_GAMMA_ENABLE;
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cntl = MCURSOR_PIPE_GAMMA_ENABLE;
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if (crtc_state->csc_enable)
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cntl |= MCURSOR_PIPE_CSC_ENABLE;
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if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
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cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
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cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
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return cntl;
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}
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@ -502,7 +502,7 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane,
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i9xx_cursor_ctl_crtc(crtc_state);
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if (width != height)
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fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
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fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
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base = intel_cursor_base(plane_state);
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pos = intel_cursor_position(plane_state);
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@ -586,13 +586,12 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
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val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
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ret = val & MCURSOR_MODE;
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ret = val & MCURSOR_MODE_MASK;
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if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
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*pipe = plane->pipe;
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else
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*pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
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MCURSOR_PIPE_SELECT_SHIFT;
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*pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
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intel_display_power_put(dev_priv, power_domain, wakeref);
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@ -10004,9 +10004,9 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
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intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
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DISPLAY_PLANE_ENABLE);
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drm_WARN_ON(&dev_priv->drm,
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intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
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intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
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drm_WARN_ON(&dev_priv->drm,
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intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
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intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
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intel_de_write(dev_priv, PIPECONF(pipe), 0);
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intel_de_posting_read(dev_priv, PIPECONF(pipe));
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@ -187,7 +187,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
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vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
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vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
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vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
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vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
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vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
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}
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@ -498,7 +498,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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for_each_pipe(dev_priv, pipe) {
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vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
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vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
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vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
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vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
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vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
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}
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@ -342,7 +342,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
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return -ENODEV;
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val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
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mode = val & MCURSOR_MODE;
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mode = val & MCURSOR_MODE_MASK;
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plane->enabled = (mode != MCURSOR_MODE_DISABLE);
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if (!plane->enabled)
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return -ENODEV;
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@ -5756,44 +5756,50 @@ enum {
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/* Cursor A & B regs */
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#define _CURACNTR 0x70080
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/* Old style CUR*CNTR flags (desktop 8xx) */
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#define CURSOR_ENABLE 0x80000000
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#define CURSOR_GAMMA_ENABLE 0x40000000
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#define CURSOR_STRIDE_SHIFT 28
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#define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
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#define CURSOR_FORMAT_SHIFT 24
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#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
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#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
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#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
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#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
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#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
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#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
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#define CURSOR_ENABLE REG_BIT(31)
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#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
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#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
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#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
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#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
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#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
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#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
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#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
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#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
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#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
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/* New style CUR*CNTR flags */
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#define MCURSOR_MODE 0x27
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#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
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#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
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#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
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#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
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#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
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#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
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#define MCURSOR_ROTATE_180 REG_BIT(15)
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#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
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#define MCURSOR_MODE_MASK 0x27
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#define MCURSOR_MODE_DISABLE 0x00
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#define MCURSOR_MODE_128_32B_AX 0x02
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#define MCURSOR_MODE_256_32B_AX 0x03
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#define MCURSOR_MODE_64_32B_AX 0x07
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#define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
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#define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
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#define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
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#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
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#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
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#define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
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#define MCURSOR_PIPE_SELECT_SHIFT 28
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#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
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#define MCURSOR_GAMMA_ENABLE (1 << 26)
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#define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
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#define MCURSOR_ROTATE_180 (1 << 15)
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#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
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#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
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#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
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#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
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#define _CURABASE 0x70084
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#define _CURAPOS 0x70088
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#define CURSOR_POS_MASK 0x007FF
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#define CURSOR_POS_SIGN 0x8000
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#define CURSOR_X_SHIFT 0
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#define CURSOR_Y_SHIFT 16
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#define CURSIZE _MMIO(0x700a0) /* 845/865 */
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#define CURSOR_POS_Y_SIGN REG_BIT(31)
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#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
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#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
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#define CURSOR_POS_X_SIGN REG_BIT(15)
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#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
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#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
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#define _CURASIZE 0x700a0 /* 845/865 */
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#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
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#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
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#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
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#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
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#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
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#define CUR_FBC_CTL_EN (1 << 31)
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#define CUR_FBC_EN REG_BIT(31)
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#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
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#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
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#define _CURASURFLIVE 0x700ac /* g4x+ */
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#define _CURBCNTR 0x700c0
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#define _CURBBASE 0x700c4
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@ -5806,6 +5812,7 @@ enum {
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#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
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#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
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#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
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#define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE)
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#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
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#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
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