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drm/amdgpu: turn on/off uvd clock when dpm enable/disable on CI
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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415282b15e
commit
3495a10357
1 changed files with 16 additions and 4 deletions
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@ -887,9 +887,6 @@ static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
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{
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struct ci_power_info *pi = ci_get_pi(adev);
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if (pi->uvd_power_gated == gate)
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return;
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pi->uvd_power_gated = gate;
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ci_update_uvd_dpm(adev, gate);
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@ -4201,8 +4198,15 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
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{
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struct ci_power_info *pi = ci_get_pi(adev);
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u32 tmp;
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int ret = 0;
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if (!gate) {
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/* turn the clocks on when decoding */
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ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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AMD_CG_STATE_UNGATE);
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if (ret)
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return ret;
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if (pi->caps_uvd_dpm ||
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(adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
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pi->smc_state_table.UvdBootLevel = 0;
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@ -4214,9 +4218,17 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
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tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
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tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
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WREG32_SMC(ixDPM_TABLE_475, tmp);
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ret = ci_enable_uvd_dpm(adev, true);
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} else {
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ret = ci_enable_uvd_dpm(adev, false);
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if (ret)
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return ret;
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ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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AMD_CG_STATE_GATE);
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}
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return ci_enable_uvd_dpm(adev, !gate);
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return ret;
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}
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static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
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