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clk: samsung: exynos5420: Set ID for aclk333 gate clock 

The aclk333 clock needs to be ungated during the MFC power domain switch,
so set the clock ID to allow the Exynos power domain logic to lookup this
clock if is defined in the MFC PD device tree node.

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Javier Martinez Canillas 2016-05-24 13:41:01 -04:00 committed by Sylwester Nawrocki
parent 41743a19b6
commit 34cba90037
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/samsung/clk-exynos5420.c
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@ -946,7 +946,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
GATE_BUS_TOP, 13, 0, 0),
GATE(0, "aclk166", "mout_user_aclk166",
GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
GATE(0, "aclk333", "mout_user_aclk333",
GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
GATE_BUS_TOP, 16, 0, 0),