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Documentation: binding: Modify the exynos5440 PCIe binding
According to using PHY framework, updates the exynos5440-pcie binding. For maintaining backward compatibility, leaves the current dt-binding. (It should be deprecated.) Recommends to use the PHY Framework and "config" property to follow the designware-pcie binding. If you use the old way, can see "missing *config* reg space" message. Because the getting configuration space address from range is old way. NOTE: When use the "config" property, first name of 'reg-names' must be set to "elbi". Otherwise driver can't maintain the backward capability. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Rob Herring <robh@kernel.org>
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@ -7,8 +7,19 @@ Required properties:
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- compatible: "samsung,exynos5440-pcie"
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- reg: base addresses and lengths of the pcie controller,
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the phy controller, additional register for the phy controller.
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(Registers for the phy controller are DEPRECATED.
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Use the PHY framework.)
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- reg-names : First name should be set to "elbi".
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And use the "config" instead of getting the confgiruation address space
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from "ranges".
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NOTE: When use the "config" property, reg-names must be set.
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- interrupts: A list of interrupt outputs for level interrupt,
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pulse interrupt, special interrupt.
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- phys: From PHY binding. Phandle for the Generic PHY.
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Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
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Other common properties refer to
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Documentation/devicetree/binding/pci/designware-pcie.txt
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Example:
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@ -54,6 +65,24 @@ SoC specific DT Entry:
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num-lanes = <4>;
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};
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With using PHY framework:
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pcie_phy0: pcie-phy@270000 {
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...
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reg = <0x270000 0x1000>, <0x271000 0x40>;
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reg-names = "phy", "block";
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...
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};
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pcie@290000 {
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...
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reg = <0x290000 0x1000>, <0x40000000 0x1000>;
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reg-names = "elbi", "config";
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phys = <&pcie_phy0>;
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ranges = <0x81000000 0 0 0x60001000 0 0x00010000
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0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
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...
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};
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Board specific DT Entry:
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pcie@290000 {
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