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PCI: xgene: Convert to use generic config accessors
Convert the xgene host PCI driver to use the generic config access functions. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Tanmay Inamdar <tinamdar@apm.com> CC: linux-arm-kernel@lists.infradead.org
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0e7ac8de01
commit
350f8be5bb
1 changed files with 9 additions and 141 deletions
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@ -74,92 +74,6 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
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return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
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}
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/* PCIe Configuration Out/In */
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static inline void xgene_pcie_cfg_out32(void __iomem *addr, int offset, u32 val)
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{
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writel(val, addr + offset);
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}
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static inline void xgene_pcie_cfg_out16(void __iomem *addr, int offset, u16 val)
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{
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u32 val32 = readl(addr + (offset & ~0x3));
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switch (offset & 0x3) {
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case 2:
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val32 &= ~0xFFFF0000;
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val32 |= (u32)val << 16;
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break;
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case 0:
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default:
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val32 &= ~0xFFFF;
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val32 |= val;
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break;
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}
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writel(val32, addr + (offset & ~0x3));
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}
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static inline void xgene_pcie_cfg_out8(void __iomem *addr, int offset, u8 val)
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{
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u32 val32 = readl(addr + (offset & ~0x3));
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switch (offset & 0x3) {
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case 0:
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val32 &= ~0xFF;
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val32 |= val;
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break;
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case 1:
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val32 &= ~0xFF00;
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val32 |= (u32)val << 8;
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break;
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case 2:
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val32 &= ~0xFF0000;
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val32 |= (u32)val << 16;
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break;
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case 3:
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default:
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val32 &= ~0xFF000000;
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val32 |= (u32)val << 24;
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break;
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}
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writel(val32, addr + (offset & ~0x3));
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}
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static inline void xgene_pcie_cfg_in32(void __iomem *addr, int offset, u32 *val)
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{
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*val = readl(addr + offset);
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}
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static inline void xgene_pcie_cfg_in16(void __iomem *addr, int offset, u32 *val)
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{
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*val = readl(addr + (offset & ~0x3));
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switch (offset & 0x3) {
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case 2:
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*val >>= 16;
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break;
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}
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*val &= 0xFFFF;
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}
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static inline void xgene_pcie_cfg_in8(void __iomem *addr, int offset, u32 *val)
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{
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*val = readl(addr + (offset & ~0x3));
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switch (offset & 0x3) {
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case 3:
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*val = *val >> 24;
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break;
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case 2:
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*val = *val >> 16;
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break;
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case 1:
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*val = *val >> 8;
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break;
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}
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*val &= 0xFF;
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}
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/*
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* When the address bit [17:16] is 2'b01, the Configuration access will be
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* treated as Type 1 and it will be forwarded to external PCIe device.
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@ -213,69 +127,23 @@ static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
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return false;
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}
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static int xgene_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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static int xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
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int offset)
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{
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struct xgene_pcie_port *port = bus->sysdata;
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void __iomem *addr;
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if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (xgene_pcie_hide_rc_bars(bus, offset)) {
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*val = 0;
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return PCIBIOS_SUCCESSFUL;
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}
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if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up ||
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xgene_pcie_hide_rc_bars(bus, offset))
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return NULL;
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xgene_pcie_set_rtdid_reg(bus, devfn);
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addr = xgene_pcie_get_cfg_base(bus);
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switch (len) {
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case 1:
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xgene_pcie_cfg_in8(addr, offset, val);
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break;
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case 2:
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xgene_pcie_cfg_in16(addr, offset, val);
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break;
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default:
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xgene_pcie_cfg_in32(addr, offset, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int xgene_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct xgene_pcie_port *port = bus->sysdata;
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void __iomem *addr;
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if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (xgene_pcie_hide_rc_bars(bus, offset))
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return PCIBIOS_SUCCESSFUL;
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xgene_pcie_set_rtdid_reg(bus, devfn);
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addr = xgene_pcie_get_cfg_base(bus);
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switch (len) {
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case 1:
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xgene_pcie_cfg_out8(addr, offset, (u8)val);
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break;
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case 2:
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xgene_pcie_cfg_out16(addr, offset, (u16)val);
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break;
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default:
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xgene_pcie_cfg_out32(addr, offset, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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return xgene_pcie_get_cfg_base(bus);
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}
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static struct pci_ops xgene_pcie_ops = {
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.read = xgene_pcie_read_config,
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.write = xgene_pcie_write_config
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.map_bus = xgene_pcie_map_bus,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write32,
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};
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static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
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