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spi: sunxi: Add Allwinner A31 SPI controller driver
The Allwinner A31 has a new SPI controller IP compared to the older Allwinner SoCs. It supports DMA, but the driver only does PIO for now, and DMA will be supported eventually. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
parent
38dbfb59d1
commit
3558fe900e
4 changed files with 514 additions and 0 deletions
24
Documentation/devicetree/bindings/spi/spi-sun6i.txt
Normal file
24
Documentation/devicetree/bindings/spi/spi-sun6i.txt
Normal file
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@ -0,0 +1,24 @@
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Allwinner A31 SPI controller
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Required properties:
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- compatible: Should be "allwinner,sun6i-a31-spi".
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- reg: Should contain register location and length.
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- interrupts: Should contain interrupt.
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- clocks: phandle to the clocks feeding the SPI controller. Two are
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needed:
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- "ahb": the gated AHB parent clock
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- "mod": the parent module clock
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- clock-names: Must contain the clock names described just above
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- resets: phandle to the reset controller asserting this device in
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reset
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Example:
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spi1: spi@01c69000 {
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compatible = "allwinner,sun6i-a31-spi";
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reg = <0x01c69000 0x1000>;
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interrupts = <0 66 4>;
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clocks = <&ahb1_gates 21>, <&spi1_clk>;
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clock-names = "ahb", "mod";
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resets = <&ahb1_rst 21>;
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};
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@ -446,6 +446,12 @@ config SPI_SIRF
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help
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SPI driver for CSR SiRFprimaII SoCs
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config SPI_SUN6I
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tristate "Allwinner A31 SPI controller"
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depends on ARCH_SUNXI || COMPILE_TEST
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help
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This enables using the SPI controller on the Allwinner A31 SoCs.
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config SPI_MXS
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tristate "Freescale MXS SPI controller"
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depends on ARCH_MXS
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@ -70,6 +70,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
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obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
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obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
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obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
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obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
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obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
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obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
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483
drivers/spi/spi-sun6i.c
Normal file
483
drivers/spi/spi-sun6i.c
Normal file
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@ -0,0 +1,483 @@
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/*
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* Copyright (C) 2012 - 2014 Allwinner Tech
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* Pan Nan <pannan@allwinnertech.com>
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*
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* Copyright (C) 2014 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/workqueue.h>
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#include <linux/spi/spi.h>
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#define SUN6I_FIFO_DEPTH 128
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#define SUN6I_GBL_CTL_REG 0x04
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#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
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#define SUN6I_GBL_CTL_MASTER BIT(1)
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#define SUN6I_GBL_CTL_TP BIT(7)
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#define SUN6I_GBL_CTL_RST BIT(31)
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#define SUN6I_TFR_CTL_REG 0x08
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#define SUN6I_TFR_CTL_CPHA BIT(0)
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#define SUN6I_TFR_CTL_CPOL BIT(1)
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#define SUN6I_TFR_CTL_SPOL BIT(2)
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#define SUN6I_TFR_CTL_CS_MASK 0x3
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#define SUN6I_TFR_CTL_CS(cs) (((cs) & SUN6I_TFR_CTL_CS_MASK) << 4)
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#define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
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#define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
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#define SUN6I_TFR_CTL_DHB BIT(8)
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#define SUN6I_TFR_CTL_FBS BIT(12)
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#define SUN6I_TFR_CTL_XCH BIT(31)
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#define SUN6I_INT_CTL_REG 0x10
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#define SUN6I_INT_CTL_RF_OVF BIT(8)
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#define SUN6I_INT_CTL_TC BIT(12)
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#define SUN6I_INT_STA_REG 0x14
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#define SUN6I_FIFO_CTL_REG 0x18
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#define SUN6I_FIFO_CTL_RF_RST BIT(15)
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#define SUN6I_FIFO_CTL_TF_RST BIT(31)
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#define SUN6I_FIFO_STA_REG 0x1c
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#define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
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#define SUN6I_FIFO_STA_RF_CNT_BITS 0
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#define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
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#define SUN6I_FIFO_STA_TF_CNT_BITS 16
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#define SUN6I_CLK_CTL_REG 0x24
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#define SUN6I_CLK_CTL_CDR2_MASK 0xff
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#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
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#define SUN6I_CLK_CTL_CDR1_MASK 0xf
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#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
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#define SUN6I_CLK_CTL_DRS BIT(12)
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#define SUN6I_BURST_CNT_REG 0x30
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#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff)
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#define SUN6I_XMIT_CNT_REG 0x34
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#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
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#define SUN6I_BURST_CTL_CNT_REG 0x38
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#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff)
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#define SUN6I_TXDATA_REG 0x200
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#define SUN6I_RXDATA_REG 0x300
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struct sun6i_spi {
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struct spi_master *master;
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void __iomem *base_addr;
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struct clk *hclk;
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struct clk *mclk;
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struct reset_control *rstc;
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struct completion done;
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const u8 *tx_buf;
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u8 *rx_buf;
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int len;
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};
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static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
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{
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return readl(sspi->base_addr + reg);
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}
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static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
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{
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writel(value, sspi->base_addr + reg);
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}
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static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
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{
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u32 reg, cnt;
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u8 byte;
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/* See how much data is available */
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reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
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reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
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cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
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if (len > cnt)
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len = cnt;
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while (len--) {
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byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
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if (sspi->rx_buf)
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*sspi->rx_buf++ = byte;
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}
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}
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static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
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{
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u8 byte;
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if (len > sspi->len)
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len = sspi->len;
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while (len--) {
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byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
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writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
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sspi->len--;
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}
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}
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static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
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{
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struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
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u32 reg;
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reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
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reg &= ~SUN6I_TFR_CTL_CS_MASK;
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reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
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if (enable)
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reg |= SUN6I_TFR_CTL_CS_LEVEL;
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else
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reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
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sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
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}
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static int sun6i_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *tfr)
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{
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struct sun6i_spi *sspi = spi_master_get_devdata(master);
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unsigned int mclk_rate, div, timeout;
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unsigned int tx_len = 0;
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int ret = 0;
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u32 reg;
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/* We don't support transfer larger than the FIFO */
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if (tfr->len > SUN6I_FIFO_DEPTH)
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return -EINVAL;
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reinit_completion(&sspi->done);
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sspi->tx_buf = tfr->tx_buf;
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sspi->rx_buf = tfr->rx_buf;
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sspi->len = tfr->len;
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/* Clear pending interrupts */
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sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
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/* Reset FIFO */
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sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
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SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
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/*
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* Setup the transfer control register: Chip Select,
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* polarities, etc.
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*/
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reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
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if (spi->mode & SPI_CPOL)
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reg |= SUN6I_TFR_CTL_CPOL;
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else
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reg &= ~SUN6I_TFR_CTL_CPOL;
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if (spi->mode & SPI_CPHA)
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reg |= SUN6I_TFR_CTL_CPHA;
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else
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reg &= ~SUN6I_TFR_CTL_CPHA;
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if (spi->mode & SPI_LSB_FIRST)
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reg |= SUN6I_TFR_CTL_FBS;
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else
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reg &= ~SUN6I_TFR_CTL_FBS;
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/*
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* If it's a TX only transfer, we don't want to fill the RX
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* FIFO with bogus data
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*/
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if (sspi->rx_buf)
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reg &= ~SUN6I_TFR_CTL_DHB;
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else
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reg |= SUN6I_TFR_CTL_DHB;
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/* We want to control the chip select manually */
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reg |= SUN6I_TFR_CTL_CS_MANUAL;
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sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
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/* Ensure that we have a parent clock fast enough */
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mclk_rate = clk_get_rate(sspi->mclk);
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if (mclk_rate < (2 * spi->max_speed_hz)) {
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clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
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mclk_rate = clk_get_rate(sspi->mclk);
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}
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/*
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* Setup clock divider.
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*
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* We have two choices there. Either we can use the clock
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* divide rate 1, which is calculated thanks to this formula:
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* SPI_CLK = MOD_CLK / (2 ^ cdr)
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* Or we can use CDR2, which is calculated with the formula:
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* SPI_CLK = MOD_CLK / (2 * (cdr + 1))
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* Wether we use the former or the latter is set through the
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* DRS bit.
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*
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* First try CDR2, and if we can't reach the expected
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* frequency, fall back to CDR1.
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*/
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div = mclk_rate / (2 * spi->max_speed_hz);
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if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
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if (div > 0)
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div--;
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reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
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} else {
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div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
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reg = SUN6I_CLK_CTL_CDR1(div);
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}
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sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
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/* Setup the transfer now... */
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if (sspi->tx_buf)
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tx_len = tfr->len;
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/* Setup the counters */
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sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
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sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
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sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
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SUN6I_BURST_CTL_CNT_STC(tx_len));
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/* Fill the TX FIFO */
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sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
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/* Enable the interrupts */
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
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/* Start the transfer */
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reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
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sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
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timeout = wait_for_completion_timeout(&sspi->done,
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msecs_to_jiffies(1000));
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if (!timeout) {
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ret = -ETIMEDOUT;
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goto out;
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}
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sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
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out:
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
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return ret;
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}
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static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
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{
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struct sun6i_spi *sspi = dev_id;
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u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
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/* Transfer complete */
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if (status & SUN6I_INT_CTL_TC) {
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sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
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complete(&sspi->done);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int sun6i_spi_runtime_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct sun6i_spi *sspi = spi_master_get_devdata(master);
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int ret;
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ret = clk_prepare_enable(sspi->hclk);
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if (ret) {
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dev_err(dev, "Couldn't enable AHB clock\n");
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goto out;
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}
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ret = clk_prepare_enable(sspi->mclk);
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if (ret) {
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dev_err(dev, "Couldn't enable module clock\n");
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goto err;
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}
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ret = reset_control_deassert(sspi->rstc);
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if (ret) {
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dev_err(dev, "Couldn't deassert the device from reset\n");
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goto err2;
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}
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sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
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SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
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return 0;
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err2:
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clk_disable_unprepare(sspi->mclk);
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err:
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clk_disable_unprepare(sspi->hclk);
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out:
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return ret;
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}
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static int sun6i_spi_runtime_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct sun6i_spi *sspi = spi_master_get_devdata(master);
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reset_control_assert(sspi->rstc);
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clk_disable_unprepare(sspi->mclk);
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clk_disable_unprepare(sspi->hclk);
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return 0;
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}
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static int sun6i_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct sun6i_spi *sspi;
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struct resource *res;
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int ret = 0, irq;
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master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
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if (!master) {
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dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
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return -ENOMEM;
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}
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platform_set_drvdata(pdev, master);
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sspi = spi_master_get_devdata(master);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(sspi->base_addr)) {
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ret = PTR_ERR(sspi->base_addr);
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goto err_free_master;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "No spi IRQ specified\n");
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ret = -ENXIO;
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goto err_free_master;
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}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
|
||||
0, "sun6i-spi", sspi);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Cannot request IRQ\n");
|
||||
goto err_free_master;
|
||||
}
|
||||
|
||||
sspi->master = master;
|
||||
master->set_cs = sun6i_spi_set_cs;
|
||||
master->transfer_one = sun6i_spi_transfer_one;
|
||||
master->num_chipselect = 4;
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
master->auto_runtime_pm = true;
|
||||
|
||||
sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
|
||||
if (IS_ERR(sspi->hclk)) {
|
||||
dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
|
||||
ret = PTR_ERR(sspi->hclk);
|
||||
goto err_free_master;
|
||||
}
|
||||
|
||||
sspi->mclk = devm_clk_get(&pdev->dev, "mod");
|
||||
if (IS_ERR(sspi->mclk)) {
|
||||
dev_err(&pdev->dev, "Unable to acquire module clock\n");
|
||||
ret = PTR_ERR(sspi->mclk);
|
||||
goto err_free_master;
|
||||
}
|
||||
|
||||
init_completion(&sspi->done);
|
||||
|
||||
sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(sspi->rstc)) {
|
||||
dev_err(&pdev->dev, "Couldn't get reset controller\n");
|
||||
ret = PTR_ERR(sspi->rstc);
|
||||
goto err_free_master;
|
||||
}
|
||||
|
||||
/*
|
||||
* This wake-up/shutdown pattern is to be able to have the
|
||||
* device woken up, even if runtime_pm is disabled
|
||||
*/
|
||||
ret = sun6i_spi_runtime_resume(&pdev->dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Couldn't resume the device\n");
|
||||
goto err_free_master;
|
||||
}
|
||||
|
||||
pm_runtime_set_active(&pdev->dev);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_idle(&pdev->dev);
|
||||
|
||||
ret = devm_spi_register_master(&pdev->dev, master);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "cannot register SPI master\n");
|
||||
goto err_pm_disable;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_pm_disable:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
sun6i_spi_runtime_suspend(&pdev->dev);
|
||||
err_free_master:
|
||||
spi_master_put(master);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sun6i_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id sun6i_spi_match[] = {
|
||||
{ .compatible = "allwinner,sun6i-a31-spi", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sun6i_spi_match);
|
||||
|
||||
static const struct dev_pm_ops sun6i_spi_pm_ops = {
|
||||
.runtime_resume = sun6i_spi_runtime_resume,
|
||||
.runtime_suspend = sun6i_spi_runtime_suspend,
|
||||
};
|
||||
|
||||
static struct platform_driver sun6i_spi_driver = {
|
||||
.probe = sun6i_spi_probe,
|
||||
.remove = sun6i_spi_remove,
|
||||
.driver = {
|
||||
.name = "sun6i-spi",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = sun6i_spi_match,
|
||||
.pm = &sun6i_spi_pm_ops,
|
||||
},
|
||||
};
|
||||
module_platform_driver(sun6i_spi_driver);
|
||||
|
||||
MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
|
||||
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
|
||||
MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
|
||||
MODULE_LICENSE("GPL");
|
Loading…
Reference in a new issue