powerpc/sstep: Add testcases for VSX vector paired load/store instructions
Add testcases for VSX vector paired load/store instructions. Sample o/p: emulate_step_test: lxvp : PASS emulate_step_test: stxvp : PASS emulate_step_test: lxvpx : PASS emulate_step_test: stxvpx : PASS emulate_step_test: plxvp : PASS emulate_step_test: pstxvp : PASS Signed-off-by: Balamuruhan S <bala24@linux.ibm.com> Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20201011050908.72173-6-ravi.bangoria@linux.ibm.com
This commit is contained in:
Balamuruhan S
Michael Ellerman
parent
6ce73ba769
commit
35785b293d
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@ -612,6 +612,273 @@ static void __init test_lxvd2x_stxvd2x(void)
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}
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#endif /* CONFIG_VSX */
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#ifdef CONFIG_VSX
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static void __init test_lxvp_stxvp(void)
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{
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struct pt_regs regs;
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union {
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vector128 a;
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u32 b[4];
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} c[2];
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u32 cached_b[8];
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int stepped = -1;
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if (!cpu_has_feature(CPU_FTR_ARCH_31)) {
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show_result("lxvp", "SKIP (!CPU_FTR_ARCH_31)");
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show_result("stxvp", "SKIP (!CPU_FTR_ARCH_31)");
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return;
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}
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init_pt_regs(®s);
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/*** lxvp ***/
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cached_b[0] = c[0].b[0] = 18233;
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cached_b[1] = c[0].b[1] = 34863571;
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cached_b[2] = c[0].b[2] = 834;
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cached_b[3] = c[0].b[3] = 6138911;
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cached_b[4] = c[1].b[0] = 1234;
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cached_b[5] = c[1].b[1] = 5678;
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cached_b[6] = c[1].b[2] = 91011;
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cached_b[7] = c[1].b[3] = 121314;
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regs.gpr[4] = (unsigned long)&c[0].a;
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/*
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* lxvp XTp,DQ(RA)
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* XTp = 32xTX + 2xTp
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* let TX=1 Tp=1 RA=4 DQ=0
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*/
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stepped = emulate_step(®s, ppc_inst(PPC_RAW_LXVP(34, 4, 0)));
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if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) {
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show_result("lxvp", "PASS");
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} else {
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if (!cpu_has_feature(CPU_FTR_VSX))
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show_result("lxvp", "PASS (!CPU_FTR_VSX)");
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else
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show_result("lxvp", "FAIL");
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}
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/*** stxvp ***/
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c[0].b[0] = 21379463;
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c[0].b[1] = 87;
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c[0].b[2] = 374234;
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c[0].b[3] = 4;
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c[1].b[0] = 90;
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c[1].b[1] = 122;
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c[1].b[2] = 555;
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c[1].b[3] = 32144;
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/*
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* stxvp XSp,DQ(RA)
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* XSp = 32xSX + 2xSp
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* let SX=1 Sp=1 RA=4 DQ=0
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*/
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stepped = emulate_step(®s, ppc_inst(PPC_RAW_STXVP(34, 4, 0)));
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if (stepped == 1 && cached_b[0] == c[0].b[0] && cached_b[1] == c[0].b[1] &&
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cached_b[2] == c[0].b[2] && cached_b[3] == c[0].b[3] &&
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cached_b[4] == c[1].b[0] && cached_b[5] == c[1].b[1] &&
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cached_b[6] == c[1].b[2] && cached_b[7] == c[1].b[3] &&
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cpu_has_feature(CPU_FTR_VSX)) {
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show_result("stxvp", "PASS");
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} else {
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if (!cpu_has_feature(CPU_FTR_VSX))
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show_result("stxvp", "PASS (!CPU_FTR_VSX)");
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else
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show_result("stxvp", "FAIL");
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}
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}
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#else
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static void __init test_lxvp_stxvp(void)
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{
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show_result("lxvp", "SKIP (CONFIG_VSX is not set)");
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show_result("stxvp", "SKIP (CONFIG_VSX is not set)");
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}
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#endif /* CONFIG_VSX */
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#ifdef CONFIG_VSX
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static void __init test_lxvpx_stxvpx(void)
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{
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struct pt_regs regs;
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union {
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vector128 a;
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u32 b[4];
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} c[2];
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u32 cached_b[8];
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int stepped = -1;
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if (!cpu_has_feature(CPU_FTR_ARCH_31)) {
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show_result("lxvpx", "SKIP (!CPU_FTR_ARCH_31)");
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show_result("stxvpx", "SKIP (!CPU_FTR_ARCH_31)");
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return;
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}
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init_pt_regs(®s);
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/*** lxvpx ***/
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cached_b[0] = c[0].b[0] = 18233;
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cached_b[1] = c[0].b[1] = 34863571;
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cached_b[2] = c[0].b[2] = 834;
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cached_b[3] = c[0].b[3] = 6138911;
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cached_b[4] = c[1].b[0] = 1234;
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cached_b[5] = c[1].b[1] = 5678;
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cached_b[6] = c[1].b[2] = 91011;
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cached_b[7] = c[1].b[3] = 121314;
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regs.gpr[3] = (unsigned long)&c[0].a;
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regs.gpr[4] = 0;
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/*
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* lxvpx XTp,RA,RB
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* XTp = 32xTX + 2xTp
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* let TX=1 Tp=1 RA=3 RB=4
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*/
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stepped = emulate_step(®s, ppc_inst(PPC_RAW_LXVPX(34, 3, 4)));
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if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) {
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show_result("lxvpx", "PASS");
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} else {
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if (!cpu_has_feature(CPU_FTR_VSX))
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show_result("lxvpx", "PASS (!CPU_FTR_VSX)");
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else
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show_result("lxvpx", "FAIL");
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}
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/*** stxvpx ***/
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c[0].b[0] = 21379463;
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c[0].b[1] = 87;
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c[0].b[2] = 374234;
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c[0].b[3] = 4;
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c[1].b[0] = 90;
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c[1].b[1] = 122;
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c[1].b[2] = 555;
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c[1].b[3] = 32144;
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/*
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* stxvpx XSp,RA,RB
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* XSp = 32xSX + 2xSp
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* let SX=1 Sp=1 RA=3 RB=4
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*/
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stepped = emulate_step(®s, ppc_inst(PPC_RAW_STXVPX(34, 3, 4)));
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if (stepped == 1 && cached_b[0] == c[0].b[0] && cached_b[1] == c[0].b[1] &&
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cached_b[2] == c[0].b[2] && cached_b[3] == c[0].b[3] &&
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cached_b[4] == c[1].b[0] && cached_b[5] == c[1].b[1] &&
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cached_b[6] == c[1].b[2] && cached_b[7] == c[1].b[3] &&
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cpu_has_feature(CPU_FTR_VSX)) {
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show_result("stxvpx", "PASS");
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} else {
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if (!cpu_has_feature(CPU_FTR_VSX))
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show_result("stxvpx", "PASS (!CPU_FTR_VSX)");
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else
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show_result("stxvpx", "FAIL");
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}
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}
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#else
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static void __init test_lxvpx_stxvpx(void)
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{
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show_result("lxvpx", "SKIP (CONFIG_VSX is not set)");
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show_result("stxvpx", "SKIP (CONFIG_VSX is not set)");
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}
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#endif /* CONFIG_VSX */
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#ifdef CONFIG_VSX
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static void __init test_plxvp_pstxvp(void)
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{
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struct ppc_inst instr;
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struct pt_regs regs;
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union {
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vector128 a;
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u32 b[4];
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} c[2];
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u32 cached_b[8];
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int stepped = -1;
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if (!cpu_has_feature(CPU_FTR_ARCH_31)) {
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show_result("plxvp", "SKIP (!CPU_FTR_ARCH_31)");
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show_result("pstxvp", "SKIP (!CPU_FTR_ARCH_31)");
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return;
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}
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/*** plxvp ***/
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cached_b[0] = c[0].b[0] = 18233;
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cached_b[1] = c[0].b[1] = 34863571;
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cached_b[2] = c[0].b[2] = 834;
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cached_b[3] = c[0].b[3] = 6138911;
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cached_b[4] = c[1].b[0] = 1234;
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cached_b[5] = c[1].b[1] = 5678;
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cached_b[6] = c[1].b[2] = 91011;
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cached_b[7] = c[1].b[3] = 121314;
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init_pt_regs(®s);
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regs.gpr[3] = (unsigned long)&c[0].a;
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/*
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* plxvp XTp,D(RA),R
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* XTp = 32xTX + 2xTp
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* let RA=3 R=0 D=d0||d1=0 R=0 Tp=1 TX=1
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*/
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instr = ppc_inst_prefix(PPC_RAW_PLXVP(34, 0, 3, 0) >> 32,
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PPC_RAW_PLXVP(34, 0, 3, 0) & 0xffffffff);
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stepped = emulate_step(®s, instr);
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if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) {
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show_result("plxvp", "PASS");
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} else {
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if (!cpu_has_feature(CPU_FTR_VSX))
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show_result("plxvp", "PASS (!CPU_FTR_VSX)");
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else
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show_result("plxvp", "FAIL");
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}
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/*** pstxvp ***/
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c[0].b[0] = 21379463;
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c[0].b[1] = 87;
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c[0].b[2] = 374234;
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c[0].b[3] = 4;
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c[1].b[0] = 90;
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c[1].b[1] = 122;
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c[1].b[2] = 555;
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c[1].b[3] = 32144;
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/*
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* pstxvp XSp,D(RA),R
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* XSp = 32xSX + 2xSp
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* let RA=3 D=d0||d1=0 R=0 Sp=1 SX=1
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*/
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instr = ppc_inst_prefix(PPC_RAW_PSTXVP(34, 0, 3, 0) >> 32,
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PPC_RAW_PSTXVP(34, 0, 3, 0) & 0xffffffff);
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stepped = emulate_step(®s, instr);
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if (stepped == 1 && cached_b[0] == c[0].b[0] && cached_b[1] == c[0].b[1] &&
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cached_b[2] == c[0].b[2] && cached_b[3] == c[0].b[3] &&
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cached_b[4] == c[1].b[0] && cached_b[5] == c[1].b[1] &&
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cached_b[6] == c[1].b[2] && cached_b[7] == c[1].b[3] &&
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cpu_has_feature(CPU_FTR_VSX)) {
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show_result("pstxvp", "PASS");
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} else {
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if (!cpu_has_feature(CPU_FTR_VSX))
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show_result("pstxvp", "PASS (!CPU_FTR_VSX)");
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else
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show_result("pstxvp", "FAIL");
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}
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}
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#else
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static void __init test_plxvp_pstxvp(void)
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{
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show_result("plxvp", "SKIP (CONFIG_VSX is not set)");
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show_result("pstxvp", "SKIP (CONFIG_VSX is not set)");
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}
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#endif /* CONFIG_VSX */
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static void __init run_tests_load_store(void)
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{
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test_ld();
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@ -628,6 +895,9 @@ static void __init run_tests_load_store(void)
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test_plfd_pstfd();
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test_lvx_stvx();
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test_lxvd2x_stxvd2x();
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test_lxvp_stxvp();
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test_lxvpx_stxvpx();
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test_plxvp_pstxvp();
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}
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struct compute_test {
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