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clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flags to avoid hang during S2R

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Some clocks are required to be unmasked during suspend to RAM. Otherwise
the PMU will stuck and the power down sequence will never be completed.

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
[s.nawrocki@samsung.com: edited the patch's summary]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Jonghwa Lee 2016-06-10 13:56:31 +09:00 committed by Sylwester Nawrocki
parent 7d058bc4e6
commit 358c9b952d
1 changed files with 22 additions and 12 deletions
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34
drivers/clk/samsung/clk-exynos5433.c
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@ -670,11 +670,14 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
@ -835,7 +838,7 @@ static const struct samsung_div_clock cpif_div_clks[] __initconst = {
static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
/* ENABLE_SCLK_CPIF */
GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
ENABLE_SCLK_CPIF, 9, 0, 0),
ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
ENABLE_SCLK_CPIF, 4, 0, 0),
};
@ -1442,11 +1445,13 @@ static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
/* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
@ -1676,11 +1681,14 @@ static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
ENABLE_SCLK_PERIC, 2,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
ENABLE_SCLK_PERIC, 1,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
ENABLE_SCLK_PERIC, 0,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info peric_cmu_info __initconst = {
@ -2964,7 +2972,7 @@ static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
/* ENABLE_SCLK_AUD0 */
GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
2, 0, 0),
2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
ENABLE_SCLK_AUD0, 1, 0, 0),
GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
@ -3358,9 +3366,11 @@ static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL, 3, 0, 0),
GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",