accel/ivpu: Introduce a new DRM driver for Intel VPU
VPU stands for Versatile Processing Unit and it's a CPU-integrated
inference accelerator for Computer Vision and Deep Learning
applications.
The VPU device consist of following components:
- Buttress - provides CPU to VPU integration, interrupt, frequency and
power management.
- Memory Management Unit (based on ARM MMU-600) - translates VPU to
host DMA addresses, isolates user workloads.
- RISC based microcontroller - executes firmware that provides job
execution API for the kernel-mode driver
- Neural Compute Subsystem (NCS) - does the actual work, provides
Compute and Copy engines.
- Network on Chip (NoC) - network fabric connecting all the components
This driver supports VPU IP v2.7 integrated into Intel Meteor Lake
client CPUs (14th generation).
Module sources are at drivers/accel/ivpu and module name is
"intel_vpu.ko".
This patch includes only very besic functionality:
- module, PCI device and IRQ initialization
- register definitions and low level register manipulation functions
- SET/GET_PARAM ioctls
- power up without firmware
Co-developed-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com>
Signed-off-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20230117092723.60441-2-jacek.lawrynowicz@linux.intel.com
This commit is contained in:
Jacek Lawrynowicz
Daniel Vetter
parent
6f84981772
commit
35b137630f
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@ -6894,6 +6894,15 @@ T: git https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/accel.git
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F: Documentation/accel/
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F: drivers/accel/
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DRM ACCEL DRIVERS FOR INTEL VPU
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M: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
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M: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
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L: dri-devel@lists.freedesktop.org
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S: Supported
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T: git git://anongit.freedesktop.org/drm/drm-misc
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F: drivers/accel/ivpu/
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F: include/uapi/drm/ivpu_accel.h
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DRM DRIVERS FOR ALLWINNER A10
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M: Maxime Ripard <mripard@kernel.org>
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M: Chen-Yu Tsai <wens@csie.org>
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@ -189,3 +189,4 @@ obj-$(CONFIG_COUNTER) += counter/
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obj-$(CONFIG_MOST) += most/
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obj-$(CONFIG_PECI) += peci/
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obj-$(CONFIG_HTE) += hte/
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obj-$(CONFIG_DRM_ACCEL) += accel/
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@ -22,3 +22,5 @@ menuconfig DRM_ACCEL
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major number than GPUs, and will be exposed to user-space using
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different device files, called accel/accel* (in /dev, sysfs
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and debugfs).
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source "drivers/accel/ivpu/Kconfig"
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-y += ivpu/
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@ -0,0 +1,15 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config DRM_ACCEL_IVPU
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tristate "Intel VPU for Meteor Lake and newer"
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depends on DRM_ACCEL
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depends on X86_64 && !UML
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depends on PCI && PCI_MSI
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select FW_LOADER
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select SHMEM
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help
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Choose this option if you have a system that has an 14th generation Intel CPU
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or newer. VPU stands for Versatile Processing Unit and it's a CPU-integrated
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inference accelerator for Computer Vision and Deep Learning applications.
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If "M" is selected, the module will be called intel_vpu.
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@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# Copyright (C) 2023 Intel Corporation
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intel_vpu-y := \
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ivpu_drv.o \
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ivpu_hw_mtl.o
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obj-$(CONFIG_DRM_ACCEL_IVPU) += intel_vpu.o
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@ -0,0 +1,11 @@
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- Move to threaded_irqs to mitigate potential infinite loop in ivpu_ipc_irq_handler()
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- Implement support for BLOB IDs
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- Add debugfs support to improve debugging and testing
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- Add tracing events for performance debugging
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- Implement HW based scheduling support
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- Use syncobjs for submit/sync
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- Refactor IPC protocol to improve message latency
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- Implement BO cache and MADVISE IOCTL
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- Add support for user allocated buffers using prime import and dma-buf heaps
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- Refactor struct ivpu_bo to use struct drm_gem_shmem_object
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- Add driver/device documentation
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@ -0,0 +1,353 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020-2023 Intel Corporation
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*/
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <drm/drm_accel.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_file.h>
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#include <drm/drm_gem.h>
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#include <drm/drm_ioctl.h>
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#include "ivpu_drv.h"
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#include "ivpu_hw.h"
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#ifndef DRIVER_VERSION_STR
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#define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \
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__stringify(DRM_IVPU_DRIVER_MINOR) "."
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#endif
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static const struct drm_driver driver;
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int ivpu_dbg_mask;
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module_param_named(dbg_mask, ivpu_dbg_mask, int, 0644);
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MODULE_PARM_DESC(dbg_mask, "Driver debug mask. See IVPU_DBG_* macros.");
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u8 ivpu_pll_min_ratio;
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module_param_named(pll_min_ratio, ivpu_pll_min_ratio, byte, 0644);
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MODULE_PARM_DESC(pll_min_ratio, "Minimum PLL ratio used to set VPU frequency");
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u8 ivpu_pll_max_ratio = U8_MAX;
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module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644);
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MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set VPU frequency");
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struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv)
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{
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kref_get(&file_priv->ref);
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return file_priv;
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}
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static void file_priv_release(struct kref *ref)
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{
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struct ivpu_file_priv *file_priv = container_of(ref, struct ivpu_file_priv, ref);
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kfree(file_priv);
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}
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void ivpu_file_priv_put(struct ivpu_file_priv **link)
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{
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struct ivpu_file_priv *file_priv = *link;
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WARN_ON(!file_priv);
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*link = NULL;
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kref_put(&file_priv->ref, file_priv_release);
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}
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static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
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{
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struct ivpu_file_priv *file_priv = file->driver_priv;
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struct ivpu_device *vdev = file_priv->vdev;
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struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
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struct drm_ivpu_param *args = data;
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int ret = 0;
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switch (args->param) {
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case DRM_IVPU_PARAM_DEVICE_ID:
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args->value = pdev->device;
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break;
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case DRM_IVPU_PARAM_DEVICE_REVISION:
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args->value = pdev->revision;
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break;
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case DRM_IVPU_PARAM_PLATFORM_TYPE:
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args->value = vdev->platform;
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break;
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case DRM_IVPU_PARAM_CORE_CLOCK_RATE:
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args->value = ivpu_hw_reg_pll_freq_get(vdev);
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break;
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case DRM_IVPU_PARAM_NUM_CONTEXTS:
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args->value = ivpu_get_context_count(vdev);
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break;
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case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
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args->value = vdev->hw->ranges.user_low.start;
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break;
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case DRM_IVPU_PARAM_CONTEXT_PRIORITY:
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args->value = file_priv->priority;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int ivpu_set_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
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{
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struct ivpu_file_priv *file_priv = file->driver_priv;
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struct drm_ivpu_param *args = data;
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int ret = 0;
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switch (args->param) {
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case DRM_IVPU_PARAM_CONTEXT_PRIORITY:
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if (args->value <= DRM_IVPU_CONTEXT_PRIORITY_REALTIME)
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file_priv->priority = args->value;
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else
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ret = -EINVAL;
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static int ivpu_open(struct drm_device *dev, struct drm_file *file)
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{
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struct ivpu_device *vdev = to_ivpu_device(dev);
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struct ivpu_file_priv *file_priv;
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file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
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if (!file_priv)
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return -ENOMEM;
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file_priv->vdev = vdev;
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file_priv->priority = DRM_IVPU_CONTEXT_PRIORITY_NORMAL;
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kref_init(&file_priv->ref);
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file->driver_priv = file_priv;
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return 0;
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}
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static void ivpu_postclose(struct drm_device *dev, struct drm_file *file)
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{
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struct ivpu_file_priv *file_priv = file->driver_priv;
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ivpu_file_priv_put(&file_priv);
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}
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static const struct drm_ioctl_desc ivpu_drm_ioctls[] = {
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DRM_IOCTL_DEF_DRV(IVPU_GET_PARAM, ivpu_get_param_ioctl, 0),
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DRM_IOCTL_DEF_DRV(IVPU_SET_PARAM, ivpu_set_param_ioctl, 0),
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};
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int ivpu_shutdown(struct ivpu_device *vdev)
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{
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int ret;
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ivpu_hw_irq_disable(vdev);
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ret = ivpu_hw_power_down(vdev);
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if (ret)
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ivpu_warn(vdev, "Failed to power down HW: %d\n", ret);
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return ret;
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}
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static const struct file_operations ivpu_fops = {
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.owner = THIS_MODULE,
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.mmap = drm_gem_mmap,
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DRM_ACCEL_FOPS,
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};
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static const struct drm_driver driver = {
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.driver_features = DRIVER_GEM | DRIVER_COMPUTE_ACCEL,
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.open = ivpu_open,
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.postclose = ivpu_postclose,
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.ioctls = ivpu_drm_ioctls,
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.num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
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.fops = &ivpu_fops,
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.name = DRIVER_NAME,
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.desc = DRIVER_DESC,
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.date = DRIVER_DATE,
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.major = DRM_IVPU_DRIVER_MAJOR,
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.minor = DRM_IVPU_DRIVER_MINOR,
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};
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static int ivpu_irq_init(struct ivpu_device *vdev)
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{
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struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
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int ret;
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ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
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if (ret < 0) {
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ivpu_err(vdev, "Failed to allocate a MSI IRQ: %d\n", ret);
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return ret;
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}
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vdev->irq = pci_irq_vector(pdev, 0);
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ret = devm_request_irq(vdev->drm.dev, vdev->irq, vdev->hw->ops->irq_handler,
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IRQF_NO_AUTOEN, DRIVER_NAME, vdev);
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if (ret)
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ivpu_err(vdev, "Failed to request an IRQ %d\n", ret);
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return ret;
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}
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static int ivpu_pci_init(struct ivpu_device *vdev)
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{
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struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
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struct resource *bar0 = &pdev->resource[0];
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struct resource *bar4 = &pdev->resource[4];
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int ret;
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ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0);
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vdev->regv = devm_ioremap_resource(vdev->drm.dev, bar0);
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if (IS_ERR(vdev->regv)) {
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ivpu_err(vdev, "Failed to map bar 0: %pe\n", vdev->regv);
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return PTR_ERR(vdev->regv);
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}
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ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4);
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vdev->regb = devm_ioremap_resource(vdev->drm.dev, bar4);
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if (IS_ERR(vdev->regb)) {
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ivpu_err(vdev, "Failed to map bar 4: %pe\n", vdev->regb);
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return PTR_ERR(vdev->regb);
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}
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ret = dma_set_mask_and_coherent(vdev->drm.dev, DMA_BIT_MASK(38));
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if (ret) {
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ivpu_err(vdev, "Failed to set DMA mask: %d\n", ret);
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return ret;
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}
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/* Clear any pending errors */
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pcie_capability_clear_word(pdev, PCI_EXP_DEVSTA, 0x3f);
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ret = pcim_enable_device(pdev);
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if (ret) {
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ivpu_err(vdev, "Failed to enable PCI device: %d\n", ret);
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return ret;
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}
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pci_set_master(pdev);
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return 0;
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}
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static int ivpu_dev_init(struct ivpu_device *vdev)
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{
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int ret;
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vdev->hw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->hw), GFP_KERNEL);
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if (!vdev->hw)
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return -ENOMEM;
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vdev->hw->ops = &ivpu_hw_mtl_ops;
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vdev->platform = IVPU_PLATFORM_INVALID;
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vdev->context_xa_limit.min = IVPU_GLOBAL_CONTEXT_MMU_SSID + 1;
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vdev->context_xa_limit.max = IVPU_CONTEXT_LIMIT;
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xa_init_flags(&vdev->context_xa, XA_FLAGS_ALLOC);
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ret = ivpu_pci_init(vdev);
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if (ret) {
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ivpu_err(vdev, "Failed to initialize PCI device: %d\n", ret);
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goto err_xa_destroy;
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}
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ret = ivpu_irq_init(vdev);
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if (ret) {
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ivpu_err(vdev, "Failed to initialize IRQs: %d\n", ret);
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goto err_xa_destroy;
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}
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/* Init basic HW info based on buttress registers which are accessible before power up */
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ret = ivpu_hw_info_init(vdev);
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if (ret) {
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ivpu_err(vdev, "Failed to initialize HW info: %d\n", ret);
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goto err_xa_destroy;
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}
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|
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/* Power up early so the rest of init code can access VPU registers */
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ret = ivpu_hw_power_up(vdev);
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if (ret) {
|
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ivpu_err(vdev, "Failed to power up HW: %d\n", ret);
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goto err_xa_destroy;
|
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}
|
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return 0;
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err_xa_destroy:
|
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xa_destroy(&vdev->context_xa);
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return ret;
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}
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static void ivpu_dev_fini(struct ivpu_device *vdev)
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{
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ivpu_shutdown(vdev);
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drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->context_xa));
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xa_destroy(&vdev->context_xa);
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}
|
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static struct pci_device_id ivpu_pci_ids[] = {
|
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) },
|
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{ }
|
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};
|
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MODULE_DEVICE_TABLE(pci, ivpu_pci_ids);
|
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|
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static int ivpu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
|
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struct ivpu_device *vdev;
|
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int ret;
|
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|
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vdev = devm_drm_dev_alloc(&pdev->dev, &driver, struct ivpu_device, drm);
|
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if (IS_ERR(vdev))
|
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return PTR_ERR(vdev);
|
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|
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pci_set_drvdata(pdev, vdev);
|
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|
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ret = ivpu_dev_init(vdev);
|
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if (ret) {
|
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dev_err(&pdev->dev, "Failed to initialize VPU device: %d\n", ret);
|
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return ret;
|
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}
|
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|
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ret = drm_dev_register(&vdev->drm, 0);
|
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if (ret) {
|
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dev_err(&pdev->dev, "Failed to register DRM device: %d\n", ret);
|
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ivpu_dev_fini(vdev);
|
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}
|
||||
|
||||
return ret;
|
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}
|
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|
||||
static void ivpu_remove(struct pci_dev *pdev)
|
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{
|
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struct ivpu_device *vdev = pci_get_drvdata(pdev);
|
||||
|
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drm_dev_unregister(&vdev->drm);
|
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ivpu_dev_fini(vdev);
|
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}
|
||||
|
||||
static struct pci_driver ivpu_pci_driver = {
|
||||
.name = KBUILD_MODNAME,
|
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.id_table = ivpu_pci_ids,
|
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.probe = ivpu_probe,
|
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.remove = ivpu_remove,
|
||||
};
|
||||
|
||||
module_pci_driver(ivpu_pci_driver);
|
||||
|
||||
MODULE_AUTHOR("Intel Corporation");
|
||||
MODULE_DESCRIPTION(DRIVER_DESC);
|
||||
MODULE_LICENSE("GPL and additional rights");
|
||||
MODULE_VERSION(DRIVER_VERSION_STR);
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020-2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __IVPU_DRV_H__
|
||||
#define __IVPU_DRV_H__
|
||||
|
||||
#include <drm/drm_device.h>
|
||||
#include <drm/drm_managed.h>
|
||||
#include <drm/drm_mm.h>
|
||||
#include <drm/drm_print.h>
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <linux/xarray.h>
|
||||
#include <uapi/drm/ivpu_accel.h>
|
||||
|
||||
#define DRIVER_NAME "intel_vpu"
|
||||
#define DRIVER_DESC "Driver for Intel Versatile Processing Unit (VPU)"
|
||||
#define DRIVER_DATE "20230117"
|
||||
|
||||
#define PCI_DEVICE_ID_MTL 0x7d1d
|
||||
|
||||
#define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
|
||||
#define IVPU_CONTEXT_LIMIT 64
|
||||
#define IVPU_NUM_ENGINES 2
|
||||
|
||||
#define IVPU_PLATFORM_SILICON 0
|
||||
#define IVPU_PLATFORM_SIMICS 2
|
||||
#define IVPU_PLATFORM_FPGA 3
|
||||
#define IVPU_PLATFORM_INVALID 8
|
||||
|
||||
#define IVPU_DBG_REG BIT(0)
|
||||
#define IVPU_DBG_IRQ BIT(1)
|
||||
#define IVPU_DBG_MMU BIT(2)
|
||||
#define IVPU_DBG_FILE BIT(3)
|
||||
#define IVPU_DBG_MISC BIT(4)
|
||||
#define IVPU_DBG_FW_BOOT BIT(5)
|
||||
#define IVPU_DBG_PM BIT(6)
|
||||
#define IVPU_DBG_IPC BIT(7)
|
||||
#define IVPU_DBG_BO BIT(8)
|
||||
#define IVPU_DBG_JOB BIT(9)
|
||||
#define IVPU_DBG_JSM BIT(10)
|
||||
#define IVPU_DBG_KREF BIT(11)
|
||||
#define IVPU_DBG_RPM BIT(12)
|
||||
|
||||
#define ivpu_err(vdev, fmt, ...) \
|
||||
drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
|
||||
|
||||
#define ivpu_err_ratelimited(vdev, fmt, ...) \
|
||||
drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
|
||||
|
||||
#define ivpu_warn(vdev, fmt, ...) \
|
||||
drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
|
||||
|
||||
#define ivpu_warn_ratelimited(vdev, fmt, ...) \
|
||||
drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
|
||||
|
||||
#define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
|
||||
|
||||
#define ivpu_dbg(vdev, type, fmt, args...) do { \
|
||||
if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
|
||||
dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
|
||||
} while (0)
|
||||
|
||||
#define IVPU_WA(wa_name) (vdev->wa.wa_name)
|
||||
|
||||
struct ivpu_wa_table {
|
||||
bool punit_disabled;
|
||||
bool clear_runtime_mem;
|
||||
};
|
||||
|
||||
struct ivpu_hw_info;
|
||||
|
||||
struct ivpu_device {
|
||||
struct drm_device drm;
|
||||
void __iomem *regb;
|
||||
void __iomem *regv;
|
||||
u32 platform;
|
||||
u32 irq;
|
||||
|
||||
struct ivpu_wa_table wa;
|
||||
struct ivpu_hw_info *hw;
|
||||
|
||||
struct xarray context_xa;
|
||||
struct xa_limit context_xa_limit;
|
||||
|
||||
struct {
|
||||
int boot;
|
||||
int jsm;
|
||||
int tdr;
|
||||
int reschedule_suspend;
|
||||
} timeout;
|
||||
};
|
||||
|
||||
/*
|
||||
* file_priv has its own refcount (ref) that allows user space to close the fd
|
||||
* without blocking even if VPU is still processing some jobs.
|
||||
*/
|
||||
struct ivpu_file_priv {
|
||||
struct kref ref;
|
||||
struct ivpu_device *vdev;
|
||||
u32 priority;
|
||||
};
|
||||
|
||||
extern int ivpu_dbg_mask;
|
||||
extern u8 ivpu_pll_min_ratio;
|
||||
extern u8 ivpu_pll_max_ratio;
|
||||
|
||||
struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
|
||||
void ivpu_file_priv_put(struct ivpu_file_priv **link);
|
||||
int ivpu_shutdown(struct ivpu_device *vdev);
|
||||
|
||||
static inline bool ivpu_is_mtl(struct ivpu_device *vdev)
|
||||
{
|
||||
return to_pci_dev(vdev->drm.dev)->device == PCI_DEVICE_ID_MTL;
|
||||
}
|
||||
|
||||
static inline u8 ivpu_revision(struct ivpu_device *vdev)
|
||||
{
|
||||
return to_pci_dev(vdev->drm.dev)->revision;
|
||||
}
|
||||
|
||||
static inline u16 ivpu_device_id(struct ivpu_device *vdev)
|
||||
{
|
||||
return to_pci_dev(vdev->drm.dev)->device;
|
||||
}
|
||||
|
||||
static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
|
||||
{
|
||||
return container_of(dev, struct ivpu_device, drm);
|
||||
}
|
||||
|
||||
static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
|
||||
{
|
||||
struct xa_limit ctx_limit = vdev->context_xa_limit;
|
||||
|
||||
return (ctx_limit.max - ctx_limit.min + 1);
|
||||
}
|
||||
|
||||
static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
|
||||
{
|
||||
WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
|
||||
return vdev->platform;
|
||||
}
|
||||
|
||||
static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
|
||||
{
|
||||
return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
|
||||
}
|
||||
|
||||
static inline bool ivpu_is_simics(struct ivpu_device *vdev)
|
||||
{
|
||||
return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
|
||||
}
|
||||
|
||||
static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
|
||||
{
|
||||
return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
|
||||
}
|
||||
|
||||
#endif /* __IVPU_DRV_H__ */
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020-2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __IVPU_HW_H__
|
||||
#define __IVPU_HW_H__
|
||||
|
||||
#include "ivpu_drv.h"
|
||||
|
||||
struct ivpu_hw_ops {
|
||||
int (*info_init)(struct ivpu_device *vdev);
|
||||
int (*power_up)(struct ivpu_device *vdev);
|
||||
int (*boot_fw)(struct ivpu_device *vdev);
|
||||
int (*power_down)(struct ivpu_device *vdev);
|
||||
bool (*is_idle)(struct ivpu_device *vdev);
|
||||
void (*wdt_disable)(struct ivpu_device *vdev);
|
||||
void (*diagnose_failure)(struct ivpu_device *vdev);
|
||||
u32 (*reg_pll_freq_get)(struct ivpu_device *vdev);
|
||||
u32 (*reg_telemetry_offset_get)(struct ivpu_device *vdev);
|
||||
u32 (*reg_telemetry_size_get)(struct ivpu_device *vdev);
|
||||
u32 (*reg_telemetry_enable_get)(struct ivpu_device *vdev);
|
||||
void (*reg_db_set)(struct ivpu_device *vdev, u32 db_id);
|
||||
u32 (*reg_ipc_rx_addr_get)(struct ivpu_device *vdev);
|
||||
u32 (*reg_ipc_rx_count_get)(struct ivpu_device *vdev);
|
||||
void (*reg_ipc_tx_set)(struct ivpu_device *vdev, u32 vpu_addr);
|
||||
void (*irq_clear)(struct ivpu_device *vdev);
|
||||
void (*irq_enable)(struct ivpu_device *vdev);
|
||||
void (*irq_disable)(struct ivpu_device *vdev);
|
||||
irqreturn_t (*irq_handler)(int irq, void *ptr);
|
||||
};
|
||||
|
||||
struct ivpu_addr_range {
|
||||
resource_size_t start;
|
||||
resource_size_t end;
|
||||
};
|
||||
|
||||
struct ivpu_hw_info {
|
||||
const struct ivpu_hw_ops *ops;
|
||||
struct {
|
||||
struct ivpu_addr_range global_low;
|
||||
struct ivpu_addr_range global_high;
|
||||
struct ivpu_addr_range user_low;
|
||||
struct ivpu_addr_range user_high;
|
||||
struct ivpu_addr_range global_aliased_pio;
|
||||
} ranges;
|
||||
struct {
|
||||
u8 min_ratio;
|
||||
u8 max_ratio;
|
||||
/*
|
||||
* Pll ratio for the efficiency frequency. The VPU has optimum
|
||||
* performance to power ratio at this frequency.
|
||||
*/
|
||||
u8 pn_ratio;
|
||||
u32 profiling_freq;
|
||||
} pll;
|
||||
u32 tile_fuse;
|
||||
u32 sku;
|
||||
u16 config;
|
||||
};
|
||||
|
||||
extern const struct ivpu_hw_ops ivpu_hw_mtl_ops;
|
||||
|
||||
static inline int ivpu_hw_info_init(struct ivpu_device *vdev)
|
||||
{
|
||||
return vdev->hw->ops->info_init(vdev);
|
||||
};
|
||||
|
||||
static inline int ivpu_hw_power_up(struct ivpu_device *vdev)
|
||||
{
|
||||
ivpu_dbg(vdev, PM, "HW power up\n");
|
||||
|
||||
return vdev->hw->ops->power_up(vdev);
|
||||
};
|
||||
|
||||
static inline int ivpu_hw_boot_fw(struct ivpu_device *vdev)
|
||||
{
|
||||
return vdev->hw->ops->boot_fw(vdev);
|
||||
};
|
||||
|
||||
static inline bool ivpu_hw_is_idle(struct ivpu_device *vdev)
|
||||
{
|
||||
return vdev->hw->ops->is_idle(vdev);
|
||||
};
|
||||
|
||||
static inline int ivpu_hw_power_down(struct ivpu_device *vdev)
|
||||
{
|
||||
ivpu_dbg(vdev, PM, "HW power down\n");
|
||||
|
||||
return vdev->hw->ops->power_down(vdev);
|
||||
};
|
||||
|
||||
static inline void ivpu_hw_wdt_disable(struct ivpu_device *vdev)
|
||||
{
|
||||
vdev->hw->ops->wdt_disable(vdev);
|
||||
};
|
||||
|
||||
/* Register indirect accesses */
|
||||
static inline u32 ivpu_hw_reg_pll_freq_get(struct ivpu_device *vdev)
|
||||
{
|
||||
return vdev->hw->ops->reg_pll_freq_get(vdev);
|
||||
};
|
||||
|
||||
static inline u32 ivpu_hw_reg_telemetry_offset_get(struct ivpu_device *vdev)
|
||||
{
|
||||
return vdev->hw->ops->reg_telemetry_offset_get(vdev);
|
||||
};
|
||||
|
||||
static inline u32 ivpu_hw_reg_telemetry_size_get(struct ivpu_device *vdev)
|
||||
{
|
||||
return vdev->hw->ops->reg_telemetry_size_get(vdev);
|
||||
};
|
||||
|
||||
static inline u32 ivpu_hw_reg_telemetry_enable_get(struct ivpu_device *vdev)
|
||||
{
|
||||
return vdev->hw->ops->reg_telemetry_enable_get(vdev);
|
||||
};
|
||||
|
||||
static inline void ivpu_hw_reg_db_set(struct ivpu_device *vdev, u32 db_id)
|
||||
{
|
||||
vdev->hw->ops->reg_db_set(vdev, db_id);
|
||||
};
|
||||
|
||||
static inline u32 ivpu_hw_reg_ipc_rx_addr_get(struct ivpu_device *vdev)
|
||||
{
|
||||
return vdev->hw->ops->reg_ipc_rx_addr_get(vdev);
|
||||
};
|
||||
|
||||
static inline u32 ivpu_hw_reg_ipc_rx_count_get(struct ivpu_device *vdev)
|
||||
{
|
||||
return vdev->hw->ops->reg_ipc_rx_count_get(vdev);
|
||||
};
|
||||
|
||||
static inline void ivpu_hw_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
|
||||
{
|
||||
vdev->hw->ops->reg_ipc_tx_set(vdev, vpu_addr);
|
||||
};
|
||||
|
||||
static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev)
|
||||
{
|
||||
vdev->hw->ops->irq_clear(vdev);
|
||||
};
|
||||
|
||||
static inline void ivpu_hw_irq_enable(struct ivpu_device *vdev)
|
||||
{
|
||||
vdev->hw->ops->irq_enable(vdev);
|
||||
};
|
||||
|
||||
static inline void ivpu_hw_irq_disable(struct ivpu_device *vdev)
|
||||
{
|
||||
vdev->hw->ops->irq_disable(vdev);
|
||||
};
|
||||
|
||||
static inline void ivpu_hw_init_range(struct ivpu_addr_range *range, u64 start, u64 size)
|
||||
{
|
||||
range->start = start;
|
||||
range->end = start + size;
|
||||
}
|
||||
|
||||
static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range)
|
||||
{
|
||||
return range->end - range->start;
|
||||
}
|
||||
|
||||
static inline void ivpu_hw_diagnose_failure(struct ivpu_device *vdev)
|
||||
{
|
||||
vdev->hw->ops->diagnose_failure(vdev);
|
||||
}
|
||||
|
||||
#endif /* __IVPU_HW_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,280 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020-2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __IVPU_HW_MTL_REG_H__
|
||||
#define __IVPU_HW_MTL_REG_H__
|
||||
|
||||
#include <linux/bits.h>
|
||||
|
||||
#define MTL_BUTTRESS_INTERRUPT_TYPE 0x00000000u
|
||||
|
||||
#define MTL_BUTTRESS_INTERRUPT_STAT 0x00000004u
|
||||
#define MTL_BUTTRESS_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
|
||||
#define MTL_BUTTRESS_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
|
||||
#define MTL_BUTTRESS_INTERRUPT_STAT_UFI_ERR_MASK BIT_MASK(2)
|
||||
|
||||
#define MTL_BUTTRESS_WP_REQ_PAYLOAD0 0x00000008u
|
||||
#define MTL_BUTTRESS_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
|
||||
#define MTL_BUTTRESS_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
|
||||
|
||||
#define MTL_BUTTRESS_WP_REQ_PAYLOAD1 0x0000000cu
|
||||
#define MTL_BUTTRESS_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
|
||||
#define MTL_BUTTRESS_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
|
||||
|
||||
#define MTL_BUTTRESS_WP_REQ_PAYLOAD2 0x00000010u
|
||||
#define MTL_BUTTRESS_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
|
||||
|
||||
#define MTL_BUTTRESS_WP_REQ_CMD 0x00000014u
|
||||
#define MTL_BUTTRESS_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
|
||||
|
||||
#define MTL_BUTTRESS_WP_DOWNLOAD 0x00000018u
|
||||
#define MTL_BUTTRESS_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0)
|
||||
|
||||
#define MTL_BUTTRESS_CURRENT_PLL 0x0000001cu
|
||||
#define MTL_BUTTRESS_CURRENT_PLL_RATIO_MASK GENMASK(15, 0)
|
||||
|
||||
#define MTL_BUTTRESS_PLL_ENABLE 0x00000020u
|
||||
|
||||
#define MTL_BUTTRESS_FMIN_FUSE 0x00000024u
|
||||
#define MTL_BUTTRESS_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
|
||||
#define MTL_BUTTRESS_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
|
||||
|
||||
#define MTL_BUTTRESS_FMAX_FUSE 0x00000028u
|
||||
#define MTL_BUTTRESS_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
|
||||
|
||||
#define MTL_BUTTRESS_TILE_FUSE 0x0000002cu
|
||||
#define MTL_BUTTRESS_TILE_FUSE_VALID_MASK BIT_MASK(0)
|
||||
#define MTL_BUTTRESS_TILE_FUSE_SKU_MASK GENMASK(3, 2)
|
||||
|
||||
#define MTL_BUTTRESS_LOCAL_INT_MASK 0x00000030u
|
||||
#define MTL_BUTTRESS_GLOBAL_INT_MASK 0x00000034u
|
||||
|
||||
#define MTL_BUTTRESS_PLL_STATUS 0x00000040u
|
||||
#define MTL_BUTTRESS_PLL_STATUS_LOCK_MASK BIT_MASK(1)
|
||||
|
||||
#define MTL_BUTTRESS_VPU_STATUS 0x00000044u
|
||||
#define MTL_BUTTRESS_VPU_STATUS_READY_MASK BIT_MASK(0)
|
||||
#define MTL_BUTTRESS_VPU_STATUS_IDLE_MASK BIT_MASK(1)
|
||||
|
||||
#define MTL_BUTTRESS_VPU_D0I3_CONTROL 0x00000060u
|
||||
#define MTL_BUTTRESS_VPU_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
|
||||
#define MTL_BUTTRESS_VPU_D0I3_CONTROL_I3_MASK BIT_MASK(2)
|
||||
|
||||
#define MTL_BUTTRESS_VPU_IP_RESET 0x00000050u
|
||||
#define MTL_BUTTRESS_VPU_IP_RESET_TRIGGER_MASK BIT_MASK(0)
|
||||
|
||||
#define MTL_BUTTRESS_VPU_TELEMETRY_OFFSET 0x00000080u
|
||||
#define MTL_BUTTRESS_VPU_TELEMETRY_SIZE 0x00000084u
|
||||
#define MTL_BUTTRESS_VPU_TELEMETRY_ENABLE 0x00000088u
|
||||
|
||||
#define MTL_BUTTRESS_ATS_ERR_LOG_0 0x000000a0u
|
||||
#define MTL_BUTTRESS_ATS_ERR_LOG_1 0x000000a4u
|
||||
#define MTL_BUTTRESS_ATS_ERR_CLEAR 0x000000a8u
|
||||
|
||||
#define MTL_BUTTRESS_UFI_ERR_LOG 0x000000b0u
|
||||
#define MTL_BUTTRESS_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0)
|
||||
#define MTL_BUTTRESS_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12)
|
||||
#define MTL_BUTTRESS_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20)
|
||||
|
||||
#define MTL_BUTTRESS_UFI_ERR_CLEAR 0x000000b4u
|
||||
|
||||
#define MTL_VPU_HOST_SS_CPR_CLK_SET 0x00000084u
|
||||
#define MTL_VPU_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK BIT_MASK(1)
|
||||
#define MTL_VPU_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK BIT_MASK(10)
|
||||
#define MTL_VPU_HOST_SS_CPR_CLK_SET_MSS_MAS_MASK BIT_MASK(11)
|
||||
|
||||
#define MTL_VPU_HOST_SS_CPR_RST_SET 0x00000094u
|
||||
#define MTL_VPU_HOST_SS_CPR_RST_SET_TOP_NOC_MASK BIT_MASK(1)
|
||||
#define MTL_VPU_HOST_SS_CPR_RST_SET_DSS_MAS_MASK BIT_MASK(10)
|
||||
#define MTL_VPU_HOST_SS_CPR_RST_SET_MSS_MAS_MASK BIT_MASK(11)
|
||||
|
||||
#define MTL_VPU_HOST_SS_CPR_RST_CLR 0x00000098u
|
||||
#define MTL_VPU_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK BIT_MASK(1)
|
||||
#define MTL_VPU_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK BIT_MASK(10)
|
||||
#define MTL_VPU_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK BIT_MASK(11)
|
||||
|
||||
#define MTL_VPU_HOST_SS_HW_VERSION 0x00000108u
|
||||
#define MTL_VPU_HOST_SS_HW_VERSION_SOC_REVISION_MASK GENMASK(7, 0)
|
||||
#define MTL_VPU_HOST_SS_HW_VERSION_SOC_NUMBER_MASK GENMASK(15, 8)
|
||||
#define MTL_VPU_HOST_SS_HW_VERSION_VPU_GENERATION_MASK GENMASK(23, 16)
|
||||
|
||||
#define MTL_VPU_HOST_SS_GEN_CTRL 0x00000118u
|
||||
#define MTL_VPU_HOST_SS_GEN_CTRL_PS_MASK GENMASK(31, 29)
|
||||
|
||||
#define MTL_VPU_HOST_SS_NOC_QREQN 0x00000154u
|
||||
#define MTL_VPU_HOST_SS_NOC_QREQN_TOP_SOCMMIO_MASK BIT_MASK(0)
|
||||
|
||||
#define MTL_VPU_HOST_SS_NOC_QACCEPTN 0x00000158u
|
||||
#define MTL_VPU_HOST_SS_NOC_QACCEPTN_TOP_SOCMMIO_MASK BIT_MASK(0)
|
||||
|
||||
#define MTL_VPU_HOST_SS_NOC_QDENY 0x0000015cu
|
||||
#define MTL_VPU_HOST_SS_NOC_QDENY_TOP_SOCMMIO_MASK BIT_MASK(0)
|
||||
|
||||
#define MTL_VPU_TOP_NOC_QREQN 0x00000160u
|
||||
#define MTL_VPU_TOP_NOC_QREQN_CPU_CTRL_MASK BIT_MASK(0)
|
||||
#define MTL_VPU_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK BIT_MASK(1)
|
||||
|
||||
#define MTL_VPU_TOP_NOC_QACCEPTN 0x00000164u
|
||||
#define MTL_VPU_TOP_NOC_QACCEPTN_CPU_CTRL_MASK BIT_MASK(0)
|
||||
#define MTL_VPU_TOP_NOC_QACCEPTN_HOSTIF_L2CACHE_MASK BIT_MASK(1)
|
||||
|
||||
#define MTL_VPU_TOP_NOC_QDENY 0x00000168u
|
||||
#define MTL_VPU_TOP_NOC_QDENY_CPU_CTRL_MASK BIT_MASK(0)
|
||||
#define MTL_VPU_TOP_NOC_QDENY_HOSTIF_L2CACHE_MASK BIT_MASK(1)
|
||||
|
||||
#define MTL_VPU_HOST_SS_FW_SOC_IRQ_EN 0x00000170u
|
||||
#define MTL_VPU_HOST_SS_FW_SOC_IRQ_EN_CSS_ROM_CMX_MASK BIT_MASK(0)
|
||||
#define MTL_VPU_HOST_SS_FW_SOC_IRQ_EN_CSS_DBG_MASK BIT_MASK(1)
|
||||
#define MTL_VPU_HOST_SS_FW_SOC_IRQ_EN_CSS_CTRL_MASK BIT_MASK(2)
|
||||
#define MTL_VPU_HOST_SS_FW_SOC_IRQ_EN_DEC400_MASK BIT_MASK(3)
|
||||
#define MTL_VPU_HOST_SS_FW_SOC_IRQ_EN_MSS_NCE_MASK BIT_MASK(4)
|
||||
#define MTL_VPU_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_MASK BIT_MASK(5)
|
||||
#define MTL_VPU_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_CMX_MASK BIT_MASK(6)
|
||||
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0 0x00010210u
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0_TIMER_0_INT_MASK BIT_MASK(0)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0_TIMER_1_INT_MASK BIT_MASK(1)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0_TIMER_2_INT_MASK BIT_MASK(2)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0_TIMER_3_INT_MASK BIT_MASK(3)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0_HOST_IPC_FIFO_INT_MASK BIT_MASK(4)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0_MMU_IRQ_0_INT_MASK BIT_MASK(5)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0_MMU_IRQ_1_INT_MASK BIT_MASK(6)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0_MMU_IRQ_2_INT_MASK BIT_MASK(7)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0_NOC_FIREWALL_INT_MASK BIT_MASK(8)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_0_INT_MASK BIT_MASK(30)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_1_INT_MASK BIT_MASK(31)
|
||||
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_1 0x00010214u
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_2_INT_MASK BIT_MASK(0)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_3_INT_MASK BIT_MASK(1)
|
||||
#define MTL_VPU_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_4_INT_MASK BIT_MASK(2)
|
||||
|
||||
#define MTL_VPU_HOST_SS_ICB_CLEAR_0 0x00010220u
|
||||
#define MTL_VPU_HOST_SS_ICB_CLEAR_1 0x00010224u
|
||||
#define MTL_VPU_HOST_SS_ICB_ENABLE_0 0x00010240u
|
||||
|
||||
#define MTL_VPU_HOST_SS_TIM_IPC_FIFO_ATM 0x000200f4u
|
||||
|
||||
#define MTL_VPU_HOST_SS_TIM_IPC_FIFO_STAT 0x000200fcu
|
||||
#define MTL_VPU_HOST_SS_TIM_IPC_FIFO_STAT_READ_POINTER_MASK GENMASK(7, 0)
|
||||
#define MTL_VPU_HOST_SS_TIM_IPC_FIFO_STAT_WRITE_POINTER_MASK GENMASK(15, 8)
|
||||
#define MTL_VPU_HOST_SS_TIM_IPC_FIFO_STAT_FILL_LEVEL_MASK GENMASK(23, 16)
|
||||
#define MTL_VPU_HOST_SS_TIM_IPC_FIFO_STAT_RSVD0_MASK GENMASK(31, 24)
|
||||
|
||||
#define MTL_VPU_HOST_SS_AON_PWR_ISO_EN0 0x00030020u
|
||||
#define MTL_VPU_HOST_SS_AON_PWR_ISO_EN0_MSS_CPU_MASK BIT_MASK(3)
|
||||
|
||||
#define MTL_VPU_HOST_SS_AON_PWR_ISLAND_EN0 0x00030024u
|
||||
#define MTL_VPU_HOST_SS_AON_PWR_ISLAND_EN0_MSS_CPU_MASK BIT_MASK(3)
|
||||
|
||||
#define MTL_VPU_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0 0x00030028u
|
||||
#define MTL_VPU_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0_MSS_CPU_MASK BIT_MASK(3)
|
||||
|
||||
#define MTL_VPU_HOST_SS_AON_PWR_ISLAND_STATUS0 0x0003002cu
|
||||
#define MTL_VPU_HOST_SS_AON_PWR_ISLAND_STATUS0_MSS_CPU_MASK BIT_MASK(3)
|
||||
|
||||
#define MTL_VPU_HOST_SS_AON_VPU_IDLE_GEN 0x00030200u
|
||||
#define MTL_VPU_HOST_SS_AON_VPU_IDLE_GEN_EN_MASK BIT_MASK(0)
|
||||
|
||||
#define MTL_VPU_HOST_SS_AON_DPU_ACTIVE 0x00030204u
|
||||
#define MTL_VPU_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK BIT_MASK(0)
|
||||
|
||||
#define MTL_VPU_HOST_SS_LOADING_ADDRESS_LO 0x00041040u
|
||||
#define MTL_VPU_HOST_SS_LOADING_ADDRESS_LO_DONE_MASK BIT_MASK(0)
|
||||
#define MTL_VPU_HOST_SS_LOADING_ADDRESS_LO_IOSF_RS_ID_MASK GENMASK(2, 1)
|
||||
#define MTL_VPU_HOST_SS_LOADING_ADDRESS_LO_IMAGE_LOCATION_MASK GENMASK(31, 3)
|
||||
|
||||
#define MTL_VPU_HOST_SS_WORKPOINT_CONFIG_MIRROR 0x00082020u
|
||||
#define MTL_VPU_HOST_SS_WORKPOINT_CONFIG_MIRROR_FINAL_PLL_FREQ_MASK GENMASK(15, 0)
|
||||
#define MTL_VPU_HOST_SS_WORKPOINT_CONFIG_MIRROR_CONFIG_ID_MASK GENMASK(31, 16)
|
||||
|
||||
#define MTL_VPU_HOST_MMU_IDR0 0x00200000u
|
||||
#define MTL_VPU_HOST_MMU_IDR1 0x00200004u
|
||||
#define MTL_VPU_HOST_MMU_IDR3 0x0020000cu
|
||||
#define MTL_VPU_HOST_MMU_IDR5 0x00200014u
|
||||
#define MTL_VPU_HOST_MMU_CR0 0x00200020u
|
||||
#define MTL_VPU_HOST_MMU_CR0ACK 0x00200024u
|
||||
#define MTL_VPU_HOST_MMU_CR1 0x00200028u
|
||||
#define MTL_VPU_HOST_MMU_CR2 0x0020002cu
|
||||
#define MTL_VPU_HOST_MMU_IRQ_CTRL 0x00200050u
|
||||
#define MTL_VPU_HOST_MMU_IRQ_CTRLACK 0x00200054u
|
||||
|
||||
#define MTL_VPU_HOST_MMU_GERROR 0x00200060u
|
||||
#define MTL_VPU_HOST_MMU_GERROR_CMDQ_MASK BIT_MASK(0)
|
||||
#define MTL_VPU_HOST_MMU_GERROR_EVTQ_ABT_MASK BIT_MASK(2)
|
||||
#define MTL_VPU_HOST_MMU_GERROR_PRIQ_ABT_MASK BIT_MASK(3)
|
||||
#define MTL_VPU_HOST_MMU_GERROR_MSI_CMDQ_ABT_MASK BIT_MASK(4)
|
||||
#define MTL_VPU_HOST_MMU_GERROR_MSI_EVTQ_ABT_MASK BIT_MASK(5)
|
||||
#define MTL_VPU_HOST_MMU_GERROR_MSI_PRIQ_ABT_MASK BIT_MASK(6)
|
||||
#define MTL_VPU_HOST_MMU_GERROR_MSI_ABT_MASK BIT_MASK(7)
|
||||
|
||||
#define MTL_VPU_HOST_MMU_GERRORN 0x00200064u
|
||||
|
||||
#define MTL_VPU_HOST_MMU_STRTAB_BASE 0x00200080u
|
||||
#define MTL_VPU_HOST_MMU_STRTAB_BASE_CFG 0x00200088u
|
||||
#define MTL_VPU_HOST_MMU_CMDQ_BASE 0x00200090u
|
||||
#define MTL_VPU_HOST_MMU_CMDQ_PROD 0x00200098u
|
||||
#define MTL_VPU_HOST_MMU_CMDQ_CONS 0x0020009cu
|
||||
#define MTL_VPU_HOST_MMU_EVTQ_BASE 0x002000a0u
|
||||
#define MTL_VPU_HOST_MMU_EVTQ_PROD 0x002000a8u
|
||||
#define MTL_VPU_HOST_MMU_EVTQ_CONS 0x002000acu
|
||||
#define MTL_VPU_HOST_MMU_EVTQ_PROD_SEC (0x002000a8u + SZ_64K)
|
||||
#define MTL_VPU_HOST_MMU_EVTQ_CONS_SEC (0x002000acu + SZ_64K)
|
||||
|
||||
#define MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES 0x00360000u
|
||||
#define MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES_CACHE_OVERRIDE_EN_MASK BIT_MASK(0)
|
||||
#define MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES_AWCACHE_OVERRIDE_MASK BIT_MASK(1)
|
||||
#define MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES_ARCACHE_OVERRIDE_MASK BIT_MASK(2)
|
||||
#define MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES_NOSNOOP_OVERRIDE_EN_MASK BIT_MASK(3)
|
||||
#define MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES_AW_NOSNOOP_OVERRIDE_MASK BIT_MASK(4)
|
||||
#define MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES_AR_NOSNOOP_OVERRIDE_MASK BIT_MASK(5)
|
||||
#define MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES_PTW_AW_CONTEXT_FLAG_MASK GENMASK(10, 6)
|
||||
#define MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES_PTW_AR_CONTEXT_FLAG_MASK GENMASK(15, 11)
|
||||
|
||||
#define MTL_VPU_HOST_IF_TBU_MMUSSIDV 0x00360004u
|
||||
#define MTL_VPU_HOST_IF_TBU_MMUSSIDV_TBU0_AWMMUSSIDV_MASK BIT_MASK(0)
|
||||
#define MTL_VPU_HOST_IF_TBU_MMUSSIDV_TBU0_ARMMUSSIDV_MASK BIT_MASK(1)
|
||||
#define MTL_VPU_HOST_IF_TBU_MMUSSIDV_TBU1_AWMMUSSIDV_MASK BIT_MASK(2)
|
||||
#define MTL_VPU_HOST_IF_TBU_MMUSSIDV_TBU1_ARMMUSSIDV_MASK BIT_MASK(3)
|
||||
#define MTL_VPU_HOST_IF_TBU_MMUSSIDV_TBU2_AWMMUSSIDV_MASK BIT_MASK(4)
|
||||
#define MTL_VPU_HOST_IF_TBU_MMUSSIDV_TBU2_ARMMUSSIDV_MASK BIT_MASK(5)
|
||||
#define MTL_VPU_HOST_IF_TBU_MMUSSIDV_TBU3_AWMMUSSIDV_MASK BIT_MASK(6)
|
||||
#define MTL_VPU_HOST_IF_TBU_MMUSSIDV_TBU3_ARMMUSSIDV_MASK BIT_MASK(7)
|
||||
#define MTL_VPU_HOST_IF_TBU_MMUSSIDV_TBU4_AWMMUSSIDV_MASK BIT_MASK(8)
|
||||
#define MTL_VPU_HOST_IF_TBU_MMUSSIDV_TBU4_ARMMUSSIDV_MASK BIT_MASK(9)
|
||||
|
||||
#define MTL_VPU_CPU_SS_DSU_LEON_RT_BASE 0x04000000u
|
||||
#define MTL_VPU_CPU_SS_DSU_LEON_RT_DSU_CTRL 0x04000000u
|
||||
#define MTL_VPU_CPU_SS_DSU_LEON_RT_PC_REG 0x04400010u
|
||||
#define MTL_VPU_CPU_SS_DSU_LEON_RT_NPC_REG 0x04400014u
|
||||
#define MTL_VPU_CPU_SS_DSU_LEON_RT_DSU_TRAP_REG 0x04400020u
|
||||
|
||||
#define MTL_VPU_CPU_SS_MSSCPU_CPR_CLK_SET 0x06010004u
|
||||
#define MTL_VPU_CPU_SS_MSSCPU_CPR_CLK_SET_CPU_DSU_MASK BIT_MASK(1)
|
||||
|
||||
#define MTL_VPU_CPU_SS_MSSCPU_CPR_RST_CLR 0x06010018u
|
||||
#define MTL_VPU_CPU_SS_MSSCPU_CPR_RST_CLR_CPU_DSU_MASK BIT_MASK(1)
|
||||
|
||||
#define MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC 0x06010040u
|
||||
#define MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTRUN0_MASK BIT_MASK(0)
|
||||
#define MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RESUME0_MASK BIT_MASK(1)
|
||||
#define MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTRUN1_MASK BIT_MASK(2)
|
||||
#define MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RESUME1_MASK BIT_MASK(3)
|
||||
#define MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTVEC_MASK GENMASK(31, 4)
|
||||
|
||||
#define MTL_VPU_CPU_SS_TIM_WATCHDOG 0x0602009cu
|
||||
#define MTL_VPU_CPU_SS_TIM_WDOG_EN 0x060200a4u
|
||||
#define MTL_VPU_CPU_SS_TIM_SAFE 0x060200a8u
|
||||
#define MTL_VPU_CPU_SS_TIM_IPC_FIFO 0x060200f0u
|
||||
|
||||
#define MTL_VPU_CPU_SS_TIM_GEN_CONFIG 0x06021008u
|
||||
#define MTL_VPU_CPU_SS_TIM_GEN_CONFIG_WDOG_TO_INT_CLR_MASK BIT_MASK(9)
|
||||
|
||||
#define MTL_VPU_CPU_SS_DOORBELL_0 0x06300000u
|
||||
#define MTL_VPU_CPU_SS_DOORBELL_0_SET_MASK BIT_MASK(0)
|
||||
|
||||
#define MTL_VPU_CPU_SS_DOORBELL_1 0x06301000u
|
||||
|
||||
#endif /* __IVPU_HW_MTL_REG_H__ */
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020-2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __IVPU_HW_REG_IO_H__
|
||||
#define __IVPU_HW_REG_IO_H__
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
#include "ivpu_drv.h"
|
||||
|
||||
#define REG_POLL_SLEEP_US 50
|
||||
#define REG_IO_ERROR 0xffffffff
|
||||
|
||||
#define REGB_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regb, (reg), #reg, __func__)
|
||||
#define REGB_RD32_SILENT(reg) readl(vdev->regb + (reg))
|
||||
#define REGB_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regb, (reg), #reg, __func__)
|
||||
#define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__)
|
||||
#define REGB_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regb, (reg), (val), #reg, __func__)
|
||||
|
||||
#define REGV_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regv, (reg), #reg, __func__)
|
||||
#define REGV_RD32_SILENT(reg) readl(vdev->regv + (reg))
|
||||
#define REGV_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regv, (reg), #reg, __func__)
|
||||
#define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__)
|
||||
#define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__)
|
||||
|
||||
#define REGV_WR32I(reg, stride, index, val) \
|
||||
ivpu_hw_reg_wr32_index(vdev, vdev->regv, (reg), (stride), (index), (val), #reg, __func__)
|
||||
|
||||
#define REG_FLD(REG, FLD) \
|
||||
(REG##_##FLD##_MASK)
|
||||
#define REG_FLD_NUM(REG, FLD, num) \
|
||||
FIELD_PREP(REG##_##FLD##_MASK, num)
|
||||
#define REG_GET_FLD(REG, FLD, val) \
|
||||
FIELD_GET(REG##_##FLD##_MASK, val)
|
||||
#define REG_CLR_FLD(REG, FLD, val) \
|
||||
((val) & ~(REG##_##FLD##_MASK))
|
||||
#define REG_SET_FLD(REG, FLD, val) \
|
||||
((val) | (REG##_##FLD##_MASK))
|
||||
#define REG_SET_FLD_NUM(REG, FLD, num, val) \
|
||||
(((val) & ~(REG##_##FLD##_MASK)) | FIELD_PREP(REG##_##FLD##_MASK, num))
|
||||
#define REG_TEST_FLD(REG, FLD, val) \
|
||||
((REG##_##FLD##_MASK) == ((val) & (REG##_##FLD##_MASK)))
|
||||
#define REG_TEST_FLD_NUM(REG, FLD, num, val) \
|
||||
((num) == FIELD_GET(REG##_##FLD##_MASK, val))
|
||||
|
||||
#define REGB_POLL(reg, var, cond, timeout_us) \
|
||||
read_poll_timeout(REGB_RD32_SILENT, var, cond, REG_POLL_SLEEP_US, timeout_us, false, reg)
|
||||
|
||||
#define REGV_POLL(reg, var, cond, timeout_us) \
|
||||
read_poll_timeout(REGV_RD32_SILENT, var, cond, REG_POLL_SLEEP_US, timeout_us, false, reg)
|
||||
|
||||
#define REGB_POLL_FLD(reg, fld, val, timeout_us) \
|
||||
({ \
|
||||
u32 var; \
|
||||
REGB_POLL(reg, var, (FIELD_GET(reg##_##fld##_MASK, var) == (val)), timeout_us); \
|
||||
})
|
||||
|
||||
#define REGV_POLL_FLD(reg, fld, val, timeout_us) \
|
||||
({ \
|
||||
u32 var; \
|
||||
REGV_POLL(reg, var, (FIELD_GET(reg##_##fld##_MASK, var) == (val)), timeout_us); \
|
||||
})
|
||||
|
||||
static inline u32
|
||||
ivpu_hw_reg_rd32(struct ivpu_device *vdev, void __iomem *base, u32 reg,
|
||||
const char *name, const char *func)
|
||||
{
|
||||
u32 val = readl(base + reg);
|
||||
|
||||
ivpu_dbg(vdev, REG, "%s RD: %s (0x%08x) => 0x%08x\n", func, name, reg, val);
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline u64
|
||||
ivpu_hw_reg_rd64(struct ivpu_device *vdev, void __iomem *base, u32 reg,
|
||||
const char *name, const char *func)
|
||||
{
|
||||
u64 val = readq(base + reg);
|
||||
|
||||
ivpu_dbg(vdev, REG, "%s RD: %s (0x%08x) => 0x%016llx\n", func, name, reg, val);
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void
|
||||
ivpu_hw_reg_wr32(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 val,
|
||||
const char *name, const char *func)
|
||||
{
|
||||
ivpu_dbg(vdev, REG, "%s WR: %s (0x%08x) <= 0x%08x\n", func, name, reg, val);
|
||||
writel(val, base + reg);
|
||||
}
|
||||
|
||||
static inline void
|
||||
ivpu_hw_reg_wr64(struct ivpu_device *vdev, void __iomem *base, u32 reg, u64 val,
|
||||
const char *name, const char *func)
|
||||
{
|
||||
ivpu_dbg(vdev, REG, "%s WR: %s (0x%08x) <= 0x%016llx\n", func, name, reg, val);
|
||||
writeq(val, base + reg);
|
||||
}
|
||||
|
||||
static inline void
|
||||
ivpu_hw_reg_wr32_index(struct ivpu_device *vdev, void __iomem *base, u32 reg,
|
||||
u32 stride, u32 index, u32 val, const char *name,
|
||||
const char *func)
|
||||
{
|
||||
reg += index * stride;
|
||||
|
||||
ivpu_dbg(vdev, REG, "%s WR: %s_%d (0x%08x) <= 0x%08x\n", func, name, index, reg, val);
|
||||
writel(val, base + reg);
|
||||
}
|
||||
|
||||
#endif /* __IVPU_HW_REG_IO_H__ */
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
|
||||
/*
|
||||
* Copyright (C) 2020-2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __UAPI_IVPU_DRM_H__
|
||||
#define __UAPI_IVPU_DRM_H__
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DRM_IVPU_DRIVER_MAJOR 1
|
||||
#define DRM_IVPU_DRIVER_MINOR 0
|
||||
|
||||
#define DRM_IVPU_GET_PARAM 0x00
|
||||
#define DRM_IVPU_SET_PARAM 0x01
|
||||
|
||||
#define DRM_IOCTL_IVPU_GET_PARAM \
|
||||
DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param)
|
||||
|
||||
#define DRM_IOCTL_IVPU_SET_PARAM \
|
||||
DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param)
|
||||
|
||||
/**
|
||||
* DOC: contexts
|
||||
*
|
||||
* VPU contexts have private virtual address space, job queues and priority.
|
||||
* Each context is identified by an unique ID. Context is created on open().
|
||||
*/
|
||||
|
||||
#define DRM_IVPU_PARAM_DEVICE_ID 0
|
||||
#define DRM_IVPU_PARAM_DEVICE_REVISION 1
|
||||
#define DRM_IVPU_PARAM_PLATFORM_TYPE 2
|
||||
#define DRM_IVPU_PARAM_CORE_CLOCK_RATE 3
|
||||
#define DRM_IVPU_PARAM_NUM_CONTEXTS 4
|
||||
#define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5
|
||||
#define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6
|
||||
|
||||
#define DRM_IVPU_PLATFORM_TYPE_SILICON 0
|
||||
|
||||
#define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0
|
||||
#define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1
|
||||
#define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2
|
||||
#define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3
|
||||
|
||||
/**
|
||||
* struct drm_ivpu_param - Get/Set VPU parameters
|
||||
*/
|
||||
struct drm_ivpu_param {
|
||||
/**
|
||||
* @param:
|
||||
*
|
||||
* Supported params:
|
||||
*
|
||||
* %DRM_IVPU_PARAM_DEVICE_ID:
|
||||
* PCI Device ID of the VPU device (read-only)
|
||||
*
|
||||
* %DRM_IVPU_PARAM_DEVICE_REVISION:
|
||||
* VPU device revision (read-only)
|
||||
*
|
||||
* %DRM_IVPU_PARAM_PLATFORM_TYPE:
|
||||
* Returns %DRM_IVPU_PLATFORM_TYPE_SILICON on real hardware or device specific
|
||||
* platform type when executing on a simulator or emulator (read-only)
|
||||
*
|
||||
* %DRM_IVPU_PARAM_CORE_CLOCK_RATE:
|
||||
* Current PLL frequency (read-only)
|
||||
*
|
||||
* %DRM_IVPU_PARAM_NUM_CONTEXTS:
|
||||
* Maximum number of simultaneously existing contexts (read-only)
|
||||
*
|
||||
* %DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
|
||||
* Lowest VPU virtual address available in the current context (read-only)
|
||||
*
|
||||
* %DRM_IVPU_PARAM_CONTEXT_PRIORITY:
|
||||
* Value of current context scheduling priority (read-write).
|
||||
* See DRM_IVPU_CONTEXT_PRIORITY_* for possible values.
|
||||
*
|
||||
*/
|
||||
__u32 param;
|
||||
|
||||
/** @index: Index for params that have multiple instances */
|
||||
__u32 index;
|
||||
|
||||
/** @value: Param value */
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __UAPI_IVPU_DRM_H__ */
|
||||
Loading…
Reference in New Issue