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crypto: inside-secure - Base CD fetchcount on actual CD FIFO size
This patch derives the command descriptor fetch count from the actual FIFO size advertised by the hardware. Fetching command descriptors one at a time is a performance bottleneck for small blocks, especially on hardware with multiple pipes. Even moreso if the HW has few rings. Signed-off-by: Pascal van Leeuwen <pvanleeuwen@verimatrix.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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parent
4bdf712c30
commit
35c0e6c375
2 changed files with 48 additions and 10 deletions
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@ -310,13 +310,22 @@ static int eip197_load_firmwares(struct safexcel_crypto_priv *priv)
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static int safexcel_hw_setup_cdesc_rings(struct safexcel_crypto_priv *priv)
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{
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u32 hdw, cd_size_rnd, val;
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int i;
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int i, cd_fetch_cnt;
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hdw = readl(EIP197_HIA_AIC_G(priv) + EIP197_HIA_OPTIONS);
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hdw &= GENMASK(27, 25);
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hdw >>= 25;
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cd_size_rnd = (priv->config.cd_size + (BIT(hdw) - 1)) >> hdw;
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cd_size_rnd = (priv->config.cd_size +
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(BIT(priv->hwconfig.hwdataw) - 1)) >>
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priv->hwconfig.hwdataw;
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/* determine number of CD's we can fetch into the CD FIFO as 1 block */
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if (priv->flags & SAFEXCEL_HW_EIP197) {
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/* EIP197: try to fetch enough in 1 go to keep all pipes busy */
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cd_fetch_cnt = (1 << priv->hwconfig.hwcfsize) / cd_size_rnd;
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cd_fetch_cnt = min_t(uint, cd_fetch_cnt,
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(priv->config.pes * EIP197_FETCH_DEPTH));
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} else {
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/* for the EIP97, just fetch all that fits minus 1 */
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cd_fetch_cnt = ((1 << priv->hwconfig.hwcfsize) /
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cd_size_rnd) - 1;
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}
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for (i = 0; i < priv->config.rings; i++) {
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/* ring base address */
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@ -328,8 +337,8 @@ static int safexcel_hw_setup_cdesc_rings(struct safexcel_crypto_priv *priv)
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writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.cd_offset << 16) |
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priv->config.cd_size,
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EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_DESC_SIZE);
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writel(((EIP197_FETCH_COUNT * (cd_size_rnd << hdw)) << 16) |
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(EIP197_FETCH_COUNT * priv->config.cd_offset),
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writel(((cd_fetch_cnt * (cd_size_rnd << hdw)) << 16) |
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(cd_fetch_cnt * priv->config.cd_offset),
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EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_CFG);
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/* Configure DMA tx control */
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@ -1142,7 +1151,7 @@ static int safexcel_probe_generic(void *pdev,
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int is_pci_dev)
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{
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struct device *dev = priv->dev;
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u32 peid, version, mask, val;
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u32 peid, version, mask, val, hiaopt;
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int i, ret, hwctg;
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priv->context_pool = dmam_pool_create("safexcel-context", dev,
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@ -1226,13 +1235,31 @@ static int safexcel_probe_generic(void *pdev,
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}
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priv->hwconfig.pever = EIP197_VERSION_MASK(version);
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hiaopt = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_OPTIONS);
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if (priv->flags & SAFEXCEL_HW_EIP197) {
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/* EIP197 */
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priv->hwconfig.hwdataw = (hiaopt >> EIP197_HWDATAW_OFFSET) &
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EIP197_HWDATAW_MASK;
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priv->hwconfig.hwcfsize = ((hiaopt >> EIP197_CFSIZE_OFFSET) &
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EIP197_CFSIZE_MASK) +
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EIP197_CFSIZE_ADJUST;
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} else {
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/* EIP97 */
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priv->hwconfig.hwdataw = (hiaopt >> EIP197_HWDATAW_OFFSET) &
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EIP97_HWDATAW_MASK;
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priv->hwconfig.hwcfsize = (hiaopt >> EIP97_CFSIZE_OFFSET) &
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EIP97_CFSIZE_MASK;
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}
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/* Get supported algorithms from EIP96 transform engine */
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priv->hwconfig.algo_flags = readl(EIP197_PE(priv) +
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EIP197_PE_EIP96_OPTIONS(0));
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/* Print single info line describing what we just detected */
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dev_info(priv->dev, "EIP%d:%x(%d)-HIA:%x,PE:%x,alg:%08x\n", peid,
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dev_info(priv->dev, "EIP%d:%x(%d)-HIA:%x(%d,%d),PE:%x,alg:%08x\n", peid,
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priv->hwconfig.hwver, hwctg, priv->hwconfig.hiaver,
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priv->hwconfig.hwdataw, priv->hwconfig.hwcfsize,
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priv->hwconfig.pever, priv->hwconfig.algo_flags);
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safexcel_configure(priv);
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@ -31,6 +31,7 @@
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#define EIP197_MAX_TOKENS 18
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#define EIP197_MAX_RINGS 4
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#define EIP197_FETCH_COUNT 1
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#define EIP197_FETCH_DEPTH 2
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#define EIP197_MAX_BATCH_SZ 64
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#define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \
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@ -225,6 +226,14 @@
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#define EIP197_N_PES_OFFSET 4
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#define EIP197_N_PES_MASK GENMASK(4, 0)
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#define EIP97_N_PES_MASK GENMASK(2, 0)
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#define EIP197_HWDATAW_OFFSET 25
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#define EIP197_HWDATAW_MASK GENMASK(3, 0)
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#define EIP97_HWDATAW_MASK GENMASK(2, 0)
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#define EIP197_CFSIZE_OFFSET 9
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#define EIP197_CFSIZE_ADJUST 4
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#define EIP97_CFSIZE_OFFSET 8
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#define EIP197_CFSIZE_MASK GENMASK(3, 0)
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#define EIP97_CFSIZE_MASK GENMASK(4, 0)
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/* EIP197_HIA_AIC_R_ENABLE_CTRL */
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#define EIP197_CDR_IRQ(n) BIT((n) * 2)
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@ -680,6 +689,8 @@ struct safexcel_hwconfig {
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int hwver;
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int hiaver;
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int pever;
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int hwdataw;
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int hwcfsize;
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};
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struct safexcel_crypto_priv {
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