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drm/i915/icl: Define TA_TIMING_PARAM registers
This patch defines DSI_TA_TIMING_PARAM and DPHY_TA_TIMING_PARAM registers used in dphy programming. v2: Changes (Jani N) - Define mask/shift for bitfields - Use bitfields name as per BSPEC - Define remaining bitfields Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1537095223-5184-8-git-send-email-madhav.chauhan@intel.com
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1 changed files with 23 additions and 0 deletions
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@ -10344,6 +10344,29 @@ enum skl_power_gate {
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#define HS_EXIT_MASK (0x7 << 0)
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#define HS_EXIT_SHIFT 0
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#define _DPHY_TA_TIMING_PARAM_0 0x162188
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#define _DPHY_TA_TIMING_PARAM_1 0x6c188
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#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
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_DPHY_TA_TIMING_PARAM_0,\
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_DPHY_TA_TIMING_PARAM_1)
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#define _DSI_TA_TIMING_PARAM_0 0x6b098
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#define _DSI_TA_TIMING_PARAM_1 0x6b898
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#define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
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_DSI_TA_TIMING_PARAM_0,\
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_DSI_TA_TIMING_PARAM_1)
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#define TA_SURE_OVERRIDE (1 << 31)
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#define TA_SURE(x) ((x) << 16)
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#define TA_SURE_MASK (0x1f << 16)
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#define TA_SURE_SHIFT 16
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#define TA_GO_OVERRIDE (1 << 15)
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#define TA_GO(x) ((x) << 8)
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#define TA_GO_MASK (0xf << 8)
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#define TA_GO_SHIFT 8
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#define TA_GET_OVERRIDE (1 << 7)
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#define TA_GET(x) ((x) << 0)
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#define TA_GET_MASK (0xf << 0)
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#define TA_GET_SHIFT 0
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/* bits 31:0 */
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#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
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#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
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