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accel/ivpu/37xx: Fix interrupt_clear_with_0 WA initialization
Using PCI Device ID/Revision to initialize the interrupt_clear_with_0
workaround is problematic - there are many pre-production
steppings with different behavior, even with the same PCI ID/Revision
Instead of checking for PCI Device ID/Revision, check the VPU
buttress interrupt status register behavior - if this register
is not zero after writing 1s it means there register is RW
instead of RW1C and we need to enable the interrupt_clear_with_0
workaround.
Fixes: 7f34e01f77
("accel/ivpu: Clear specific interrupt status bits on C0")
Signed-off-by: Andrzej Kacprowski <Andrzej.Kacprowski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://lore.kernel.org/all/20231204122331.40560-1-jacek.lawrynowicz@linux.intel.com
This commit is contained in:
parent
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commit
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1 changed files with 9 additions and 3 deletions
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@ -53,10 +53,12 @@
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#define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK)
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#define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK)
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#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE)) | \
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#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \
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(REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \
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(REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR)))
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(REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR)))
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#define BUTTRESS_ALL_IRQ_MASK (BUTTRESS_IRQ_MASK | \
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(REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE)))
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#define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK)
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#define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK)
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#define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
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#define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
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@ -74,8 +76,12 @@ static void ivpu_hw_wa_init(struct ivpu_device *vdev)
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vdev->wa.clear_runtime_mem = false;
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vdev->wa.clear_runtime_mem = false;
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vdev->wa.d3hot_after_power_off = true;
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vdev->wa.d3hot_after_power_off = true;
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if (ivpu_device_id(vdev) == PCI_DEVICE_ID_MTL && ivpu_revision(vdev) < 4)
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REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, BUTTRESS_ALL_IRQ_MASK);
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if (REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) == BUTTRESS_ALL_IRQ_MASK) {
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/* Writing 1s does not clear the interrupt status register */
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vdev->wa.interrupt_clear_with_0 = true;
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vdev->wa.interrupt_clear_with_0 = true;
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REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0);
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}
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IVPU_PRINT_WA(punit_disabled);
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IVPU_PRINT_WA(punit_disabled);
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IVPU_PRINT_WA(clear_runtime_mem);
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IVPU_PRINT_WA(clear_runtime_mem);
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