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KVM: PPC: Book3S HV: Set LPCR[HDICE] before writing HDEC
POWER8 and POWER9 machines have a hardware deviation where generation of a hypervisor decrementer exception is suppressed if the HDICE bit in the LPCR register is 0 at the time when the HDEC register decrements from 0 to -1. When entering a guest, KVM first writes the HDEC register with the time until it wants the CPU to exit the guest, and then writes the LPCR with the guest value, which includes HDICE = 1. If HDEC decrements from 0 to -1 during the interval between those two events, it is possible that we can enter the guest with HDEC already negative but no HDEC exception pending, meaning that no HDEC interrupt will occur while the CPU is in the guest, or at least not until HDEC wraps around. Thus it is possible for the CPU to keep executing in the guest for a long time; up to about 4 seconds on POWER8, or about 4.46 years on POWER9 (except that the host kernel hard lockup detector will fire first). To fix this, we set the LPCR[HDICE] bit before writing HDEC on guest entry. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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parent
05e6295dc7
commit
35dfb43c24
2 changed files with 18 additions and 5 deletions
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@ -3442,9 +3442,19 @@ static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu *vcpu, u64 time_limit,
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unsigned long host_psscr = mfspr(SPRN_PSSCR);
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unsigned long host_pidr = mfspr(SPRN_PID);
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/*
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* P8 and P9 suppress the HDEC exception when LPCR[HDICE] = 0,
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* so set HDICE before writing HDEC.
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*/
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mtspr(SPRN_LPCR, vcpu->kvm->arch.host_lpcr | LPCR_HDICE);
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isync();
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hdec = time_limit - mftb();
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if (hdec < 0)
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if (hdec < 0) {
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mtspr(SPRN_LPCR, vcpu->kvm->arch.host_lpcr);
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isync();
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return BOOK3S_INTERRUPT_HV_DECREMENTER;
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}
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mtspr(SPRN_HDEC, hdec);
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if (vc->tb_offset) {
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@ -3572,7 +3582,7 @@ int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
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dec = mfspr(SPRN_DEC);
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tb = mftb();
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if (dec < 512)
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if (dec < 0)
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return BOOK3S_INTERRUPT_HV_DECREMENTER;
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local_paca->kvm_hstate.dec_expires = dec + tb;
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if (local_paca->kvm_hstate.dec_expires < time_limit)
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@ -58,13 +58,16 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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/*
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* Put whatever is in the decrementer into the
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* hypervisor decrementer.
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* Because of a hardware deviation in P8 and P9,
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* we need to set LPCR[HDICE] before writing HDEC.
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*/
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BEGIN_FTR_SECTION
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ld r5, HSTATE_KVM_VCORE(r13)
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ld r6, VCORE_KVM(r5)
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ld r9, KVM_HOST_LPCR(r6)
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andis. r9, r9, LPCR_LD@h
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
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ori r8, r9, LPCR_HDICE
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mtspr SPRN_LPCR, r8
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isync
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andis. r0, r9, LPCR_LD@h
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mfspr r8,SPRN_DEC
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mftb r7
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BEGIN_FTR_SECTION
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