arm64: dts: imx8: split adma ss into dma and audio ss
amda ss is consisted of dma and audio ss in qxp which are also used in qm. Let's split them into two ss for better code reuse. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Dong Aisheng
Shawn Guo
parent
3a3e72f1ed
commit
35f4e9d753
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@ -4,245 +4,5 @@
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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adma_subsys: bus@59000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x59000000 0x0 0x59000000 0x2000000>;
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dma_ipg_clk: clock-dma-ipg {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <120000000>;
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clock-output-names = "dma_ipg_clk";
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};
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dsp_lpcg: clock-controller@59580000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59580000 0x10000>;
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#clock-cells = <1>;
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clocks = <&dma_ipg_clk>,
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<&dma_ipg_clk>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_7>;
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clock-output-names = "dsp_lpcg_adb_clk",
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"dsp_lpcg_ipg_clk",
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"dsp_lpcg_core_clk";
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power-domains = <&pd IMX_SC_R_DSP>;
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};
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dsp_ram_lpcg: clock-controller@59590000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59590000 0x10000>;
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#clock-cells = <1>;
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clocks = <&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "dsp_ram_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_DSP_RAM>;
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};
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adma_dsp: dsp@596e8000 {
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compatible = "fsl,imx8qxp-dsp";
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reg = <0x596e8000 0x88000>;
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clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
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<&dsp_ram_lpcg IMX_LPCG_CLK_4>,
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<&dsp_lpcg IMX_LPCG_CLK_7>;
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clock-names = "ipg", "ocram", "core";
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power-domains = <&pd IMX_SC_R_MU_13A>,
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<&pd IMX_SC_R_MU_13B>,
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<&pd IMX_SC_R_DSP>,
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<&pd IMX_SC_R_DSP_RAM>;
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mbox-names = "txdb0", "txdb1",
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"rxdb0", "rxdb1";
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mboxes = <&lsio_mu13 2 0>,
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<&lsio_mu13 2 1>,
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<&lsio_mu13 3 0>,
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<&lsio_mu13 3 1>;
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memory-region = <&dsp_reserved>;
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status = "disabled";
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};
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adma_lpuart0: serial@5a060000 {
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reg = <0x5a060000 0x1000>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
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<&uart0_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "baud";
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power-domains = <&pd IMX_SC_R_UART_0>;
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status = "disabled";
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};
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adma_lpuart1: serial@5a070000 {
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reg = <0x5a070000 0x1000>;
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
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<&uart1_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "baud";
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power-domains = <&pd IMX_SC_R_UART_1>;
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status = "disabled";
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};
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adma_lpuart2: serial@5a080000 {
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reg = <0x5a080000 0x1000>;
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
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<&uart2_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "baud";
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power-domains = <&pd IMX_SC_R_UART_2>;
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status = "disabled";
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};
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adma_lpuart3: serial@5a090000 {
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reg = <0x5a090000 0x1000>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
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<&uart3_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "baud";
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power-domains = <&pd IMX_SC_R_UART_3>;
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status = "disabled";
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};
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uart0_lpcg: clock-controller@5a460000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a460000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "uart0_lpcg_baud_clk",
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"uart0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_UART_0>;
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};
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uart1_lpcg: clock-controller@5a470000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a470000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "uart1_lpcg_baud_clk",
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"uart1_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_UART_1>;
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};
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uart2_lpcg: clock-controller@5a480000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a480000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "uart2_lpcg_baud_clk",
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"uart2_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_UART_2>;
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};
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uart3_lpcg: clock-controller@5a490000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a490000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "uart3_lpcg_baud_clk",
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"uart3_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_UART_3>;
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};
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adma_i2c0: i2c@5a800000 {
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reg = <0x5a800000 0x4000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>;
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clock-names = "per";
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assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_I2C_0>;
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status = "disabled";
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};
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adma_i2c1: i2c@5a810000 {
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reg = <0x5a810000 0x4000>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>;
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clock-names = "per";
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assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_I2C_1>;
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status = "disabled";
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};
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adma_i2c2: i2c@5a820000 {
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reg = <0x5a820000 0x4000>;
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>;
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clock-names = "per";
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assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_I2C_2>;
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status = "disabled";
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};
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adma_i2c3: i2c@5a830000 {
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reg = <0x5a830000 0x4000>;
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>;
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clock-names = "per";
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assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_I2C_3>;
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status = "disabled";
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};
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i2c0_lpcg: clock-controller@5ac00000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5ac00000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "i2c0_lpcg_clk",
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"i2c0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_I2C_0>;
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};
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i2c1_lpcg: clock-controller@5ac10000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5ac10000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "i2c1_lpcg_clk",
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"i2c1_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_I2C_1>;
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};
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i2c2_lpcg: clock-controller@5ac20000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5ac20000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "i2c2_lpcg_clk",
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"i2c2_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_I2C_2>;
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};
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i2c3_lpcg: clock-controller@5ac30000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5ac30000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "i2c3_lpcg_clk",
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"i2c3_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_I2C_3>;
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};
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};
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#include "imx8-ss-audio.dtsi"
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#include "imx8-ss-dma.dtsi"
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@ -0,0 +1,68 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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audio_subsys: bus@59000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x59000000 0x0 0x59000000 0x1000000>;
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audio_ipg_clk: clock-audio-ipg {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <120000000>;
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clock-output-names = "audio_ipg_clk";
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};
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dsp_lpcg: clock-controller@59580000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59580000 0x10000>;
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#clock-cells = <1>;
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clocks = <&audio_ipg_clk>,
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<&audio_ipg_clk>,
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<&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_7>;
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clock-output-names = "dsp_lpcg_adb_clk",
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"dsp_lpcg_ipg_clk",
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"dsp_lpcg_core_clk";
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power-domains = <&pd IMX_SC_R_DSP>;
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};
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dsp_ram_lpcg: clock-controller@59590000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59590000 0x10000>;
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#clock-cells = <1>;
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clocks = <&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "dsp_ram_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_DSP_RAM>;
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};
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dsp: dsp@596e8000 {
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compatible = "fsl,imx8qxp-dsp";
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reg = <0x596e8000 0x88000>;
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clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
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<&dsp_ram_lpcg IMX_LPCG_CLK_4>,
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<&dsp_lpcg IMX_LPCG_CLK_7>;
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clock-names = "ipg", "ocram", "core";
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power-domains = <&pd IMX_SC_R_MU_13A>,
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<&pd IMX_SC_R_MU_13B>,
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<&pd IMX_SC_R_DSP>,
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<&pd IMX_SC_R_DSP_RAM>;
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mbox-names = "txdb0", "txdb1",
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"rxdb0", "rxdb1";
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mboxes = <&lsio_mu13 2 0>,
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<&lsio_mu13 2 1>,
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<&lsio_mu13 3 0>,
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<&lsio_mu13 3 1>;
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memory-region = <&dsp_reserved>;
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status = "disabled";
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};
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};
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@ -0,0 +1,202 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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dma_subsys: bus@5a000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
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dma_ipg_clk: clock-dma-ipg {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <120000000>;
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clock-output-names = "dma_ipg_clk";
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};
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lpuart0: serial@5a060000 {
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reg = <0x5a060000 0x1000>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
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<&uart0_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "baud";
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power-domains = <&pd IMX_SC_R_UART_0>;
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status = "disabled";
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};
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lpuart1: serial@5a070000 {
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reg = <0x5a070000 0x1000>;
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
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<&uart1_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "baud";
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power-domains = <&pd IMX_SC_R_UART_1>;
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status = "disabled";
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};
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lpuart2: serial@5a080000 {
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reg = <0x5a080000 0x1000>;
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
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<&uart2_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "baud";
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power-domains = <&pd IMX_SC_R_UART_2>;
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status = "disabled";
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};
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lpuart3: serial@5a090000 {
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reg = <0x5a090000 0x1000>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
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<&uart3_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "baud";
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power-domains = <&pd IMX_SC_R_UART_3>;
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status = "disabled";
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};
|
||||
|
||||
uart0_lpcg: clock-controller@5a460000 {
|
||||
compatible = "fsl,imx8qxp-lpcg";
|
||||
reg = <0x5a460000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
|
||||
<&dma_ipg_clk>;
|
||||
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
|
||||
clock-output-names = "uart0_lpcg_baud_clk",
|
||||
"uart0_lpcg_ipg_clk";
|
||||
power-domains = <&pd IMX_SC_R_UART_0>;
|
||||
};
|
||||
|
||||
uart1_lpcg: clock-controller@5a470000 {
|
||||
compatible = "fsl,imx8qxp-lpcg";
|
||||
reg = <0x5a470000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
|
||||
<&dma_ipg_clk>;
|
||||
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
|
||||
clock-output-names = "uart1_lpcg_baud_clk",
|
||||
"uart1_lpcg_ipg_clk";
|
||||
power-domains = <&pd IMX_SC_R_UART_1>;
|
||||
};
|
||||
|
||||
uart2_lpcg: clock-controller@5a480000 {
|
||||
compatible = "fsl,imx8qxp-lpcg";
|
||||
reg = <0x5a480000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
|
||||
<&dma_ipg_clk>;
|
||||
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
|
||||
clock-output-names = "uart2_lpcg_baud_clk",
|
||||
"uart2_lpcg_ipg_clk";
|
||||
power-domains = <&pd IMX_SC_R_UART_2>;
|
||||
};
|
||||
|
||||
uart3_lpcg: clock-controller@5a490000 {
|
||||
compatible = "fsl,imx8qxp-lpcg";
|
||||
reg = <0x5a490000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
|
||||
<&dma_ipg_clk>;
|
||||
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
|
||||
clock-output-names = "uart3_lpcg_baud_clk",
|
||||
"uart3_lpcg_ipg_clk";
|
||||
power-domains = <&pd IMX_SC_R_UART_3>;
|
||||
};
|
||||
|
||||
i2c0: i2c@5a800000 {
|
||||
reg = <0x5a800000 0x4000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>;
|
||||
clock-names = "per";
|
||||
assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
power-domains = <&pd IMX_SC_R_I2C_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@5a810000 {
|
||||
reg = <0x5a810000 0x4000>;
|
||||
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>;
|
||||
clock-names = "per";
|
||||
assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
power-domains = <&pd IMX_SC_R_I2C_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@5a820000 {
|
||||
reg = <0x5a820000 0x4000>;
|
||||
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>;
|
||||
clock-names = "per";
|
||||
assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
power-domains = <&pd IMX_SC_R_I2C_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@5a830000 {
|
||||
reg = <0x5a830000 0x4000>;
|
||||
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>;
|
||||
clock-names = "per";
|
||||
assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
power-domains = <&pd IMX_SC_R_I2C_3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0_lpcg: clock-controller@5ac00000 {
|
||||
compatible = "fsl,imx8qxp-lpcg";
|
||||
reg = <0x5ac00000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
|
||||
<&dma_ipg_clk>;
|
||||
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
|
||||
clock-output-names = "i2c0_lpcg_clk",
|
||||
"i2c0_lpcg_ipg_clk";
|
||||
power-domains = <&pd IMX_SC_R_I2C_0>;
|
||||
};
|
||||
|
||||
i2c1_lpcg: clock-controller@5ac10000 {
|
||||
compatible = "fsl,imx8qxp-lpcg";
|
||||
reg = <0x5ac10000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
|
||||
<&dma_ipg_clk>;
|
||||
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
|
||||
clock-output-names = "i2c1_lpcg_clk",
|
||||
"i2c1_lpcg_ipg_clk";
|
||||
power-domains = <&pd IMX_SC_R_I2C_1>;
|
||||
};
|
||||
|
||||
i2c2_lpcg: clock-controller@5ac20000 {
|
||||
compatible = "fsl,imx8qxp-lpcg";
|
||||
reg = <0x5ac20000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
|
||||
<&dma_ipg_clk>;
|
||||
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
|
||||
clock-output-names = "i2c2_lpcg_clk",
|
||||
"i2c2_lpcg_ipg_clk";
|
||||
power-domains = <&pd IMX_SC_R_I2C_2>;
|
||||
};
|
||||
|
||||
i2c3_lpcg: clock-controller@5ac30000 {
|
||||
compatible = "fsl,imx8qxp-lpcg";
|
||||
reg = <0x5ac30000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
|
||||
<&dma_ipg_clk>;
|
||||
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
|
||||
clock-output-names = "i2c3_lpcg_clk",
|
||||
"i2c3_lpcg_ipg_clk";
|
||||
power-domains = <&pd IMX_SC_R_I2C_3>;
|
||||
};
|
||||
};
|
||||
|
|
@ -13,13 +13,13 @@
|
|||
compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
|
||||
|
||||
aliases {
|
||||
serial1 = &adma_lpuart1;
|
||||
serial2 = &adma_lpuart2;
|
||||
serial3 = &adma_lpuart3;
|
||||
serial1 = &lpuart1;
|
||||
serial2 = &lpuart2;
|
||||
serial3 = &lpuart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &adma_lpuart2;
|
||||
stdout-path = &lpuart2;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
|
|
@ -82,7 +82,7 @@
|
|||
};
|
||||
|
||||
/* BT */
|
||||
&adma_lpuart0 {
|
||||
&lpuart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart0>;
|
||||
uart-has-rtscts;
|
||||
|
|
@ -90,21 +90,21 @@
|
|||
};
|
||||
|
||||
/* LS-UART0 */
|
||||
&adma_lpuart1 {
|
||||
&lpuart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Debug */
|
||||
&adma_lpuart2 {
|
||||
&lpuart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* PCI-E UART */
|
||||
&adma_lpuart3 {
|
||||
&lpuart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart3>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
&adma_i2c1 {
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
/* M41T0M6 real time clock on carrier board */
|
||||
|
|
@ -37,17 +37,17 @@
|
|||
};
|
||||
|
||||
/* Colibri UART_B */
|
||||
&adma_lpuart0 {
|
||||
&lpuart0 {
|
||||
status= "okay";
|
||||
};
|
||||
|
||||
/* Colibri UART_C */
|
||||
&adma_lpuart2 {
|
||||
&lpuart2 {
|
||||
status= "okay";
|
||||
};
|
||||
|
||||
/* Colibri UART_A */
|
||||
&adma_lpuart3 {
|
||||
&lpuart3 {
|
||||
status= "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
|
||||
|
||||
chosen {
|
||||
stdout-path = &adma_lpuart3;
|
||||
stdout-path = &lpuart3;
|
||||
};
|
||||
|
||||
reg_module_3v3: regulator-module-3v3 {
|
||||
|
|
@ -22,7 +22,7 @@
|
|||
};
|
||||
|
||||
/* On-module I2C */
|
||||
&adma_i2c0 {
|
||||
&i2c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <100000>;
|
||||
|
|
@ -49,7 +49,7 @@
|
|||
};
|
||||
|
||||
/* Colibri I2C */
|
||||
&adma_i2c1 {
|
||||
&i2c1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <100000>;
|
||||
|
|
@ -58,19 +58,19 @@
|
|||
};
|
||||
|
||||
/* Colibri UART_B */
|
||||
&adma_lpuart0 {
|
||||
&lpuart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart0>;
|
||||
};
|
||||
|
||||
/* Colibri UART_C */
|
||||
&adma_lpuart2 {
|
||||
&lpuart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart2>;
|
||||
};
|
||||
|
||||
/* Colibri UART_A */
|
||||
&adma_lpuart3 {
|
||||
&lpuart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
|
||||
|
||||
chosen {
|
||||
stdout-path = &adma_lpuart0;
|
||||
stdout-path = &lpuart0;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
|
|
@ -30,11 +30,30 @@
|
|||
};
|
||||
};
|
||||
|
||||
&adma_dsp {
|
||||
&dsp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&adma_i2c1 {
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <100000>;
|
||||
|
|
@ -110,31 +129,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
&adma_lpuart0 {
|
||||
&lpuart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scu_key {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,34 +4,34 @@
|
|||
* Dong Aisheng <aisheng.dong@nxp.com>
|
||||
*/
|
||||
|
||||
&adma_lpuart0 {
|
||||
&lpuart0 {
|
||||
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
};
|
||||
|
||||
&adma_lpuart1 {
|
||||
&lpuart1 {
|
||||
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
};
|
||||
|
||||
&adma_lpuart2 {
|
||||
&lpuart2 {
|
||||
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
};
|
||||
|
||||
&adma_lpuart3 {
|
||||
&lpuart3 {
|
||||
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
};
|
||||
|
||||
&adma_i2c0 {
|
||||
&i2c0 {
|
||||
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
};
|
||||
|
||||
&adma_i2c1 {
|
||||
&i2c1 {
|
||||
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
};
|
||||
|
||||
&adma_i2c2 {
|
||||
&i2c2 {
|
||||
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
};
|
||||
|
||||
&adma_i2c3 {
|
||||
&i2c3 {
|
||||
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -30,10 +30,10 @@
|
|||
gpio5 = &lsio_gpio5;
|
||||
gpio6 = &lsio_gpio6;
|
||||
gpio7 = &lsio_gpio7;
|
||||
i2c0 = &adma_i2c0;
|
||||
i2c1 = &adma_i2c1;
|
||||
i2c2 = &adma_i2c2;
|
||||
i2c3 = &adma_i2c3;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
|
|
@ -42,10 +42,10 @@
|
|||
mu2 = &lsio_mu2;
|
||||
mu3 = &lsio_mu3;
|
||||
mu4 = &lsio_mu4;
|
||||
serial0 = &adma_lpuart0;
|
||||
serial1 = &adma_lpuart1;
|
||||
serial2 = &adma_lpuart2;
|
||||
serial3 = &adma_lpuart3;
|
||||
serial0 = &lpuart0;
|
||||
serial1 = &lpuart1;
|
||||
serial2 = &lpuart2;
|
||||
serial3 = &lpuart3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
|
|||
Loading…
Reference in New Issue