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spi/fsl-espi: make the clock computation easier to read
The -1 +1 thingy should probably do what DIV_ROUND_UP does. The 4 is 2 the "platform_clock => sysclock" and 2 from the computation part. The 64 is the same 4 times 16. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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1 changed files with 2 additions and 2 deletions
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@ -180,7 +180,7 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
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if ((mpc8xxx_spi->spibrg / hz) > 64) {
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cs->hw_mode |= CSMODE_DIV16;
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pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
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pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
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WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
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"Will use %d Hz instead.\n", dev_name(&spi->dev),
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@ -188,7 +188,7 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
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if (pm > 16)
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pm = 16;
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} else {
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pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
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pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
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}
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if (pm)
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pm--;
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