MediaTek SPI controller cleanups and documentation
Merge series from AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>: This series performs some cleanups to the spi-mt65xx driver, removing all gotos, simplifying the probe function and adding kerneldoc to the driver structures.
This commit is contained in:
Mark Brown
commit
3625a627f6
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@ -20,110 +20,139 @@
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#include <linux/spi/spi-mem.h>
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#include <linux/dma-mapping.h>
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#define SPI_CFG0_REG 0x0000
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#define SPI_CFG1_REG 0x0004
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#define SPI_TX_SRC_REG 0x0008
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#define SPI_RX_DST_REG 0x000c
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#define SPI_TX_DATA_REG 0x0010
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#define SPI_RX_DATA_REG 0x0014
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#define SPI_CMD_REG 0x0018
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#define SPI_STATUS0_REG 0x001c
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#define SPI_PAD_SEL_REG 0x0024
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#define SPI_CFG2_REG 0x0028
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#define SPI_TX_SRC_REG_64 0x002c
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#define SPI_RX_DST_REG_64 0x0030
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#define SPI_CFG3_IPM_REG 0x0040
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#define SPI_CFG0_REG 0x0000
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#define SPI_CFG1_REG 0x0004
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#define SPI_TX_SRC_REG 0x0008
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#define SPI_RX_DST_REG 0x000c
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#define SPI_TX_DATA_REG 0x0010
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#define SPI_RX_DATA_REG 0x0014
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#define SPI_CMD_REG 0x0018
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#define SPI_STATUS0_REG 0x001c
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#define SPI_PAD_SEL_REG 0x0024
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#define SPI_CFG2_REG 0x0028
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#define SPI_TX_SRC_REG_64 0x002c
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#define SPI_RX_DST_REG_64 0x0030
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#define SPI_CFG3_IPM_REG 0x0040
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#define SPI_CFG0_SCK_HIGH_OFFSET 0
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#define SPI_CFG0_SCK_LOW_OFFSET 8
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#define SPI_CFG0_CS_HOLD_OFFSET 16
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#define SPI_CFG0_CS_SETUP_OFFSET 24
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#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
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#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
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#define SPI_CFG0_SCK_HIGH_OFFSET 0
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#define SPI_CFG0_SCK_LOW_OFFSET 8
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#define SPI_CFG0_CS_HOLD_OFFSET 16
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#define SPI_CFG0_CS_SETUP_OFFSET 24
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#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
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#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
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#define SPI_CFG1_CS_IDLE_OFFSET 0
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#define SPI_CFG1_PACKET_LOOP_OFFSET 8
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#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
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#define SPI_CFG1_GET_TICK_DLY_OFFSET 29
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#define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30
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#define SPI_CFG1_CS_IDLE_OFFSET 0
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#define SPI_CFG1_PACKET_LOOP_OFFSET 8
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#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
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#define SPI_CFG1_GET_TICK_DLY_OFFSET 29
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#define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30
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#define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000
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#define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000
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#define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000
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#define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000
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#define SPI_CFG1_CS_IDLE_MASK 0xff
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#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
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#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
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#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16)
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#define SPI_CFG2_SCK_HIGH_OFFSET 0
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#define SPI_CFG2_SCK_LOW_OFFSET 16
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#define SPI_CFG1_CS_IDLE_MASK 0xff
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#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
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#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
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#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16)
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#define SPI_CFG2_SCK_HIGH_OFFSET 0
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#define SPI_CFG2_SCK_LOW_OFFSET 16
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#define SPI_CMD_ACT BIT(0)
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#define SPI_CMD_RESUME BIT(1)
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#define SPI_CMD_RST BIT(2)
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#define SPI_CMD_PAUSE_EN BIT(4)
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#define SPI_CMD_DEASSERT BIT(5)
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#define SPI_CMD_SAMPLE_SEL BIT(6)
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#define SPI_CMD_CS_POL BIT(7)
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#define SPI_CMD_CPHA BIT(8)
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#define SPI_CMD_CPOL BIT(9)
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#define SPI_CMD_RX_DMA BIT(10)
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#define SPI_CMD_TX_DMA BIT(11)
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#define SPI_CMD_TXMSBF BIT(12)
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#define SPI_CMD_RXMSBF BIT(13)
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#define SPI_CMD_RX_ENDIAN BIT(14)
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#define SPI_CMD_TX_ENDIAN BIT(15)
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#define SPI_CMD_FINISH_IE BIT(16)
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#define SPI_CMD_PAUSE_IE BIT(17)
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#define SPI_CMD_IPM_NONIDLE_MODE BIT(19)
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#define SPI_CMD_IPM_SPIM_LOOP BIT(21)
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#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22
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#define SPI_CMD_ACT BIT(0)
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#define SPI_CMD_RESUME BIT(1)
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#define SPI_CMD_RST BIT(2)
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#define SPI_CMD_PAUSE_EN BIT(4)
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#define SPI_CMD_DEASSERT BIT(5)
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#define SPI_CMD_SAMPLE_SEL BIT(6)
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#define SPI_CMD_CS_POL BIT(7)
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#define SPI_CMD_CPHA BIT(8)
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#define SPI_CMD_CPOL BIT(9)
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#define SPI_CMD_RX_DMA BIT(10)
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#define SPI_CMD_TX_DMA BIT(11)
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#define SPI_CMD_TXMSBF BIT(12)
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#define SPI_CMD_RXMSBF BIT(13)
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#define SPI_CMD_RX_ENDIAN BIT(14)
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#define SPI_CMD_TX_ENDIAN BIT(15)
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#define SPI_CMD_FINISH_IE BIT(16)
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#define SPI_CMD_PAUSE_IE BIT(17)
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#define SPI_CMD_IPM_NONIDLE_MODE BIT(19)
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#define SPI_CMD_IPM_SPIM_LOOP BIT(21)
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#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22
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#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22)
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#define PIN_MODE_CFG(x) ((x) / 2)
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#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2)
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#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3)
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#define SPI_CFG3_IPM_XMODE_EN BIT(4)
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#define SPI_CFG3_IPM_NODATA_FLAG BIT(5)
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#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8
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#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12
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#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2)
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#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3)
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#define SPI_CFG3_IPM_XMODE_EN BIT(4)
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#define SPI_CFG3_IPM_NODATA_FLAG BIT(5)
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#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8
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#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12
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#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0)
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#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8)
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#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12)
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#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0)
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#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8)
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#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12)
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#define MT8173_SPI_MAX_PAD_SEL 3
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#define MT8173_SPI_MAX_PAD_SEL 3
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#define MTK_SPI_PAUSE_INT_STATUS 0x2
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#define MTK_SPI_PAUSE_INT_STATUS 0x2
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#define MTK_SPI_IDLE 0
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#define MTK_SPI_PAUSED 1
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#define MTK_SPI_MAX_FIFO_SIZE 32U
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#define MTK_SPI_PACKET_SIZE 1024
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#define MTK_SPI_IPM_PACKET_SIZE SZ_64K
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#define MTK_SPI_IPM_PACKET_LOOP SZ_256
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#define MTK_SPI_MAX_FIFO_SIZE 32U
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#define MTK_SPI_PACKET_SIZE 1024
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#define MTK_SPI_IPM_PACKET_SIZE SZ_64K
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#define MTK_SPI_IPM_PACKET_LOOP SZ_256
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#define MTK_SPI_IDLE 0
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#define MTK_SPI_PAUSED 1
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#define MTK_SPI_32BITS_MASK (0xffffffff)
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#define MTK_SPI_32BITS_MASK (0xffffffff)
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#define DMA_ADDR_EXT_BITS (36)
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#define DMA_ADDR_DEF_BITS (32)
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#define DMA_ADDR_EXT_BITS (36)
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#define DMA_ADDR_DEF_BITS (32)
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/**
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* struct mtk_spi_compatible - device data structure
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* @need_pad_sel: Enable pad (pins) selection in SPI controller
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* @must_tx: Must explicitly send dummy TX bytes to do RX only transfer
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* @enhance_timing: Enable adjusting cfg register to enhance time accuracy
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* @dma_ext: DMA address extension supported
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* @no_need_unprepare: Don't unprepare the SPI clk during runtime
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* @ipm_design: Adjust/extend registers to support IPM design IP features
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*/
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struct mtk_spi_compatible {
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bool need_pad_sel;
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/* Must explicitly send dummy Tx bytes to do Rx only transfer */
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bool must_tx;
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/* some IC design adjust cfg register to enhance time accuracy */
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bool enhance_timing;
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/* some IC support DMA addr extension */
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bool dma_ext;
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/* some IC no need unprepare SPI clk */
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bool no_need_unprepare;
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/* IPM design adjust and extend register to support more features */
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bool ipm_design;
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};
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/**
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* struct mtk_spi - SPI driver instance
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* @base: Start address of the SPI controller registers
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* @state: SPI controller state
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* @pad_num: Number of pad_sel entries
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* @pad_sel: Groups of pins to select
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* @parent_clk: Parent of sel_clk
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* @sel_clk: SPI master mux clock
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* @spi_clk: Peripheral clock
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* @spi_hclk: AHB bus clock
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* @cur_transfer: Currently processed SPI transfer
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* @xfer_len: Number of bytes to transfer
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* @num_xfered: Number of transferred bytes
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* @tx_sgl: TX transfer scatterlist
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* @rx_sgl: RX transfer scatterlist
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* @tx_sgl_len: Size of TX DMA transfer
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* @rx_sgl_len: Size of RX DMA transfer
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* @dev_comp: Device data structure
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* @spi_clk_hz: Current SPI clock in Hz
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* @spimem_done: SPI-MEM operation completion
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* @use_spimem: Enables SPI-MEM
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* @dev: Device pointer
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* @tx_dma: DMA start for SPI-MEM TX
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* @rx_dma: DMA start for SPI-MEM RX
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*/
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struct mtk_spi {
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void __iomem *base;
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u32 state;
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@ -1082,19 +1111,17 @@ static const struct spi_controller_mem_ops mtk_spi_mem_ops = {
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static int mtk_spi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct spi_master *master;
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struct mtk_spi *mdata;
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const struct of_device_id *of_id;
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int i, irq, ret, addr_bits;
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master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
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if (!master) {
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dev_err(&pdev->dev, "failed to alloc spi master\n");
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return -ENOMEM;
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}
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master = devm_spi_alloc_master(dev, sizeof(*mdata));
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if (!master)
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return dev_err_probe(dev, -ENOMEM, "failed to alloc spi master\n");
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master->auto_runtime_pm = true;
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master->dev.of_node = pdev->dev.of_node;
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master->dev.of_node = dev->of_node;
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
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master->set_cs = mtk_spi_set_cs;
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@ -1105,15 +1132,8 @@ static int mtk_spi_probe(struct platform_device *pdev)
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master->set_cs_timing = mtk_spi_set_hw_cs_timing;
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master->use_gpio_descriptors = true;
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of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
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if (!of_id) {
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dev_err(&pdev->dev, "failed to probe of_node\n");
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ret = -EINVAL;
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goto err_put_master;
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}
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mdata = spi_master_get_devdata(master);
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mdata->dev_comp = of_id->data;
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mdata->dev_comp = device_get_match_data(dev);
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if (mdata->dev_comp->enhance_timing)
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master->mode_bits |= SPI_CS_HIGH;
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@ -1124,109 +1144,80 @@ static int mtk_spi_probe(struct platform_device *pdev)
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master->mode_bits |= SPI_LOOP;
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if (mdata->dev_comp->ipm_design) {
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mdata->dev = &pdev->dev;
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mdata->dev = dev;
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master->mem_ops = &mtk_spi_mem_ops;
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init_completion(&mdata->spimem_done);
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}
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if (mdata->dev_comp->need_pad_sel) {
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mdata->pad_num = of_property_count_u32_elems(
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pdev->dev.of_node,
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mdata->pad_num = of_property_count_u32_elems(dev->of_node,
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"mediatek,pad-select");
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if (mdata->pad_num < 0) {
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dev_err(&pdev->dev,
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if (mdata->pad_num < 0)
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return dev_err_probe(dev, -EINVAL,
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"No 'mediatek,pad-select' property\n");
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ret = -EINVAL;
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goto err_put_master;
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}
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mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
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mdata->pad_sel = devm_kmalloc_array(dev, mdata->pad_num,
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sizeof(u32), GFP_KERNEL);
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if (!mdata->pad_sel) {
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ret = -ENOMEM;
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goto err_put_master;
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}
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if (!mdata->pad_sel)
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return -ENOMEM;
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for (i = 0; i < mdata->pad_num; i++) {
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of_property_read_u32_index(pdev->dev.of_node,
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of_property_read_u32_index(dev->of_node,
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"mediatek,pad-select",
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i, &mdata->pad_sel[i]);
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if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
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dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
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i, mdata->pad_sel[i]);
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ret = -EINVAL;
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goto err_put_master;
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}
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if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL)
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return dev_err_probe(dev, -EINVAL,
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"wrong pad-sel[%d]: %u\n",
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i, mdata->pad_sel[i]);
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}
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}
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platform_set_drvdata(pdev, master);
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mdata->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mdata->base)) {
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ret = PTR_ERR(mdata->base);
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goto err_put_master;
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}
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if (IS_ERR(mdata->base))
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return PTR_ERR(mdata->base);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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ret = irq;
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goto err_put_master;
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}
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if (irq < 0)
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return irq;
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if (!pdev->dev.dma_mask)
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pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
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if (!dev->dma_mask)
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dev->dma_mask = &dev->coherent_dma_mask;
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ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
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IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
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if (ret) {
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dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
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goto err_put_master;
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}
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ret = devm_request_irq(dev, irq, mtk_spi_interrupt,
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IRQF_TRIGGER_NONE, dev_name(dev), master);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register irq\n");
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mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
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if (IS_ERR(mdata->parent_clk)) {
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ret = PTR_ERR(mdata->parent_clk);
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dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
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goto err_put_master;
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}
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mdata->parent_clk = devm_clk_get(dev, "parent-clk");
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if (IS_ERR(mdata->parent_clk))
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return dev_err_probe(dev, PTR_ERR(mdata->parent_clk),
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"failed to get parent-clk\n");
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mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
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if (IS_ERR(mdata->sel_clk)) {
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ret = PTR_ERR(mdata->sel_clk);
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dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
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goto err_put_master;
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}
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mdata->sel_clk = devm_clk_get(dev, "sel-clk");
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if (IS_ERR(mdata->sel_clk))
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return dev_err_probe(dev, PTR_ERR(mdata->sel_clk), "failed to get sel-clk\n");
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mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
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if (IS_ERR(mdata->spi_clk)) {
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ret = PTR_ERR(mdata->spi_clk);
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dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
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goto err_put_master;
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}
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mdata->spi_clk = devm_clk_get(dev, "spi-clk");
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if (IS_ERR(mdata->spi_clk))
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return dev_err_probe(dev, PTR_ERR(mdata->spi_clk), "failed to get spi-clk\n");
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mdata->spi_hclk = devm_clk_get_optional(&pdev->dev, "hclk");
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if (IS_ERR(mdata->spi_hclk)) {
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ret = PTR_ERR(mdata->spi_hclk);
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dev_err(&pdev->dev, "failed to get hclk: %d\n", ret);
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goto err_put_master;
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}
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mdata->spi_hclk = devm_clk_get_optional(dev, "hclk");
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if (IS_ERR(mdata->spi_hclk))
|
||||
return dev_err_probe(dev, PTR_ERR(mdata->spi_hclk), "failed to get hclk\n");
|
||||
|
||||
ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
|
||||
if (ret < 0)
|
||||
return dev_err_probe(dev, ret, "failed to clk_set_parent\n");
|
||||
|
||||
ret = clk_prepare_enable(mdata->spi_hclk);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to enable hclk (%d)\n", ret);
|
||||
goto err_put_master;
|
||||
}
|
||||
if (ret < 0)
|
||||
return dev_err_probe(dev, ret, "failed to enable hclk\n");
|
||||
|
||||
ret = clk_prepare_enable(mdata->spi_clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
|
||||
goto err_disable_spi_hclk;
|
||||
}
|
||||
|
||||
ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
|
||||
goto err_disable_spi_clk;
|
||||
clk_disable_unprepare(mdata->spi_hclk);
|
||||
return dev_err_probe(dev, ret, "failed to enable spi_clk\n");
|
||||
}
|
||||
|
||||
mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
|
||||
|
|
@ -1239,52 +1230,35 @@ static int mtk_spi_probe(struct platform_device *pdev)
|
|||
clk_disable_unprepare(mdata->spi_hclk);
|
||||
}
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
if (mdata->dev_comp->need_pad_sel) {
|
||||
if (mdata->pad_num != master->num_chipselect) {
|
||||
dev_err(&pdev->dev,
|
||||
if (mdata->pad_num != master->num_chipselect)
|
||||
return dev_err_probe(dev, -EINVAL,
|
||||
"pad_num does not match num_chipselect(%d != %d)\n",
|
||||
mdata->pad_num, master->num_chipselect);
|
||||
ret = -EINVAL;
|
||||
goto err_disable_runtime_pm;
|
||||
}
|
||||
|
||||
if (!master->cs_gpiods && master->num_chipselect > 1) {
|
||||
dev_err(&pdev->dev,
|
||||
if (!master->cs_gpiods && master->num_chipselect > 1)
|
||||
return dev_err_probe(dev, -EINVAL,
|
||||
"cs_gpios not specified and num_chipselect > 1\n");
|
||||
ret = -EINVAL;
|
||||
goto err_disable_runtime_pm;
|
||||
}
|
||||
}
|
||||
|
||||
if (mdata->dev_comp->dma_ext)
|
||||
addr_bits = DMA_ADDR_EXT_BITS;
|
||||
else
|
||||
addr_bits = DMA_ADDR_DEF_BITS;
|
||||
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
|
||||
ret = dma_set_mask(dev, DMA_BIT_MASK(addr_bits));
|
||||
if (ret)
|
||||
dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
|
||||
dev_notice(dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
|
||||
addr_bits, ret);
|
||||
|
||||
ret = devm_spi_register_master(&pdev->dev, master);
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
ret = devm_spi_register_master(dev, master);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
|
||||
goto err_disable_runtime_pm;
|
||||
pm_runtime_disable(dev);
|
||||
return dev_err_probe(dev, ret, "failed to register master\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_disable_runtime_pm:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
err_disable_spi_clk:
|
||||
clk_disable_unprepare(mdata->spi_clk);
|
||||
err_disable_spi_hclk:
|
||||
clk_disable_unprepare(mdata->spi_hclk);
|
||||
err_put_master:
|
||||
spi_master_put(master);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_spi_remove(struct platform_device *pdev)
|
||||
|
|
|
|||
Loading…
Reference in New Issue