More changes for omap dts files mostly to add support for
dm816x devices and clocks. Also adds a qspi device for dra72x-evm. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUvpqoAAoJEBvUPslcq6Vz2uwQALoPyfwWCDUlxZbZy/yNPq0b +l90dAo65hzrsPo9kWswj/lDfFDwTrLjxL9KcRu0gaoQp+UUgDOTuTIVe2ftqU4T 6C6MqriKlHL6vRYmm5BOrQq+Oc+xjdNSxfnCPOouOQRESJG8Jf7+5DykUkVcgh7n PeLaRLLb8AtEg0eBzRl7DtqvCJDU9zq8WkbtEeNso/j7P2uZ3DL/jieS0nyx9n14 fcHlHmNlBCAUH80DfbpU9QkfAg2G3DAahtdFFBrct/CltdbkprS3efzBGawQpRrh XBqWsFCnNz4nzAshFHgKsTmtX94mgzLj89VwvsVtVTnErlC7umbrUiPrj358F72Y lZib7jl3BLiVsDWSqIw5iulkpS+ukW1iBCzlp5C87DSXE97XJr7UscbA9EQMesFl bHcfq9cbpvMK6hujdx2QuZcSeahjvHSguIrxGtgtcf6Xj4Rx/iDGaTpalA5fxl65 VJn1FHmC74MYcpwnZSXk8KqVyX6IjlfRnc3C9Nt5GRXLx98h09l62LyIaMq2xAKv EvNoKf9T7MKo1ayhCDkja4ObcRU8HhR4v5Z32NkumbqT2jP8TjhzRGuLynMiNV1w M3Rv11D2wCo1e30vJjCpBI/cJOa6pdHFiWQrmmDI09wAywhZbmikxUJ0OIf5/H5r D+eWlZQSGWvtsRlVRkwI =vWKv -----END PGP SIGNATURE----- Merge tag 'omap-for-v3.20/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt Merge "omap device tree changes for v3.20, part 2" from Tony Lindgren: More changes for omap dts files mostly to add support for dm816x devices and clocks. Also adds a qspi device for dra72x-evm. * tag 'omap-for-v3.20/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: dra72-evm: Add qspi device ARM: dts: Add minimal support for dm8168-evm ARM: dts: Add basic clocks for dm816x ARM: dts: Add basic dm816x device tree configuration Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
362c9a778c
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@ -393,6 +393,8 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
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omap3-sbc-t3730.dtb \
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omap3-thunder.dtb \
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omap3-zoom3.dtb
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dtb-$(CONFIG_SOC_TI81XX) += \
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dm8168-evm.dtb
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dtb-$(CONFIG_SOC_AM33XX) += \
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am335x-base0033.dtb \
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am335x-bone.dtb \
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@ -0,0 +1,129 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "dm816x.dtsi"
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/ {
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model = "DM8168 EVM";
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compatible = "ti,dm8168-evm", "ti,dm8168";
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memory {
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device_type = "memory";
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reg = <0x80000000 0x40000000 /* 1 GB */
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0xc0000000 0x40000000>; /* 1 GB */
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};
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/* FDC6331L controlled by SD_POW pin */
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vmmcsd_fixed: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vmmcsd_fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&dm816x_pinmux {
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mcspi1_pins: pinmux_mcspi1_pins {
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pinctrl-single,pins = <
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DM816X_IOPAD(0x0a94, PIN_INPUT | MUX_MODE0) /* SPI_SCLK */
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DM816X_IOPAD(0x0a98, PIN_OUTPUT | MUX_MODE0) /* SPI_SCS0 */
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DM816X_IOPAD(0x0aa8, PIN_INPUT | MUX_MODE0) /* SPI_D0 */
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DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */
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>;
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};
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};
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&i2c1 {
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extgpio0: pcf8575@20 {
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compatible = "nxp,pcf8575";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&i2c2 {
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extgpio1: pcf8575@20 {
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compatible = "nxp,pcf8575";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&gpmc {
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ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
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nand@0,0 {
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linux,mtd-name= "micron,mt29f2g16aadwp";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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#address-cells = <1>;
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#size-cells = <1>;
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ti,nand-ecc-opt = "bch8";
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <44>;
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gpmc,cs-wr-off-ns = <44>;
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gpmc,adv-on-ns = <6>;
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gpmc,adv-rd-off-ns = <34>;
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gpmc,adv-wr-off-ns = <44>;
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gpmc,we-on-ns = <0>;
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gpmc,we-off-ns = <40>;
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gpmc,oe-on-ns = <0>;
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gpmc,oe-off-ns = <54>;
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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partition@0 {
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label = "X-Loader";
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reg = <0 0x80000>;
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};
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partition@0x80000 {
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label = "U-Boot";
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reg = <0x80000 0x1c0000>;
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};
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partition@0x1c0000 {
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label = "Environment";
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reg = <0x240000 0x40000>;
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};
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partition@0x280000 {
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label = "Kernel";
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reg = <0x280000 0x500000>;
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};
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partition@0x780000 {
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label = "Filesystem";
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reg = <0x780000 0xf880000>;
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};
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};
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};
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&mcspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcspi1_pins>;
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m25p80@0 {
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compatible = "w25x32";
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spi-max-frequency = <48000000>;
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&mmc1 {
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vmmc-supply = <&vmmcsd_fixed>;
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};
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@ -0,0 +1,250 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&scrm {
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main_fapll: main_fapll {
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#clock-cells = <1>;
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compatible = "ti,dm816-fapll-clock";
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reg = <0x400 0x40>;
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clocks = <&sys_clkin_ck &sys_clkin_ck>;
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clock-indices = <1>, <2>, <3>, <4>, <5>,
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<6>, <7>;
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clock-output-names = "main_pll_clk1",
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"main_pll_clk2",
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"main_pll_clk3",
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"main_pll_clk4",
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"main_pll_clk5",
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"main_pll_clk6",
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"main_pll_clk7";
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};
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ddr_fapll: ddr_fapll {
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#clock-cells = <1>;
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compatible = "ti,dm816-fapll-clock";
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reg = <0x440 0x30>;
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clocks = <&sys_clkin_ck &sys_clkin_ck>;
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clock-indices = <1>, <2>, <3>, <4>;
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clock-output-names = "ddr_pll_clk1",
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"ddr_pll_clk2",
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"ddr_pll_clk3",
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"ddr_pll_clk4";
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};
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video_fapll: video_fapll {
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#clock-cells = <1>;
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compatible = "ti,dm816-fapll-clock";
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reg = <0x470 0x30>;
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clocks = <&sys_clkin_ck &sys_clkin_ck>;
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clock-indices = <1>, <2>, <3>;
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clock-output-names = "video_pll_clk1",
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"video_pll_clk2",
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"video_pll_clk3";
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};
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audio_fapll: audio_fapll {
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#clock-cells = <1>;
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compatible = "ti,dm816-fapll-clock";
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reg = <0x4a0 0x30>;
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clocks = <&main_fapll 7>, < &sys_clkin_ck>;
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clock-indices = <1>, <2>, <3>, <4>, <5>;
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clock-output-names = "audio_pll_clk1",
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"audio_pll_clk2",
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"audio_pll_clk3",
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"audio_pll_clk4",
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"audio_pll_clk5";
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};
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};
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&scrm_clocks {
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secure_32k_ck: secure_32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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sys_32k_ck: sys_32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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tclkin_ck: tclkin_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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sys_clkin_ck: sys_clkin_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <27000000>;
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};
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};
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/* 0x48180000 */
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&prcm_clocks {
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clkout_pre_ck: clkout_pre_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
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&audio_fapll 1>;
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reg = <0x100>;
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};
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clkout_div_ck: clkout_div_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&clkout_pre_ck>;
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ti,bit-shift = <3>;
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ti,max-div = <8>;
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reg = <0x100>;
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};
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clkout_ck: clkout_ck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&clkout_div_ck>;
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ti,bit-shift = <7>;
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reg = <0x100>;
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};
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/* CM_DPLL clocks p1795 */
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sysclk1_ck: sysclk1_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&main_fapll 1>;
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ti,max-div = <7>;
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reg = <0x0300>;
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};
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sysclk2_ck: sysclk2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&main_fapll 2>;
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ti,max-div = <7>;
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reg = <0x0304>;
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};
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sysclk3_ck: sysclk3_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&main_fapll 3>;
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ti,max-div = <7>;
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reg = <0x0308>;
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};
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sysclk4_ck: sysclk4_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&main_fapll 4>;
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ti,max-div = <1>;
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reg = <0x030c>;
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};
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sysclk5_ck: sysclk5_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&sysclk4_ck>;
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ti,max-div = <1>;
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reg = <0x0310>;
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};
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sysclk6_ck: sysclk6_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&main_fapll 4>;
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ti,dividers = <2>, <4>;
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reg = <0x0314>;
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};
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sysclk10_ck: sysclk10_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&ddr_fapll 2>;
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ti,max-div = <7>;
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reg = <0x0324>;
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};
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sysclk24_ck: sysclk24_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
|
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clocks = <&main_fapll 5>;
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ti,max-div = <7>;
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reg = <0x03b4>;
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};
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|
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mpu_ck: mpu_ck {
|
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#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sysclk2_ck>;
|
||||
ti,bit-shift = <1>;
|
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reg = <0x15dc>;
|
||||
};
|
||||
|
||||
audio_pll_a_ck: audio_pll_a_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&audio_fapll 1>;
|
||||
ti,max-div = <7>;
|
||||
reg = <0x035c>;
|
||||
};
|
||||
|
||||
sysclk18_ck: sysclk18_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
|
||||
reg = <0x0378>;
|
||||
};
|
||||
|
||||
timer1_fck: timer1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0390>;
|
||||
};
|
||||
|
||||
timer2_fck: timer2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0394>;
|
||||
};
|
||||
|
||||
timer3_fck: timer3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0398>;
|
||||
};
|
||||
|
||||
timer4_fck: timer4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x039c>;
|
||||
};
|
||||
|
||||
timer5_fck: timer5_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x03a0>;
|
||||
};
|
||||
|
||||
timer6_fck: timer6_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x03a4>;
|
||||
};
|
||||
|
||||
timer7_fck: timer7_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x03a8>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,387 @@
|
|||
/*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/omap.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,dm816";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a8";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a8-pmu";
|
||||
interrupts = <3>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap3-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
||||
};
|
||||
|
||||
dm816x_pinmux: pinmux@44e10800 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x48140800 0x50a>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0xf>;
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the dm816x interconnect.
|
||||
* The real dm816x interconnect network is quite complex. Since
|
||||
* it will not bring real advantage to represent that in DT
|
||||
* for the moment, just use a fake OCP bus entry to represent
|
||||
* the whole bus hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "ti,omap3-l3-smx", "simple-bus";
|
||||
reg = <0x44000000 0x10000>;
|
||||
interrupts = <9 10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main";
|
||||
|
||||
prcm: prcm@48180000 {
|
||||
compatible = "ti,dm816-prcm";
|
||||
reg = <0x48180000 0x4000>;
|
||||
|
||||
prcm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prcm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scrm: scrm@48140000 {
|
||||
compatible = "ti,dm816-scrm";
|
||||
reg = <0x48140000 0x21000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x48140000 0x21000>;
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
cm: syscon@44e10000 {
|
||||
compatible = "ti,am33xx-controlmodule", "syscon";
|
||||
reg = <0x44e10000 0x800>;
|
||||
};
|
||||
|
||||
edma: edma@49000000 {
|
||||
compatible = "ti,edma3";
|
||||
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
|
||||
reg = <0x49000000 0x10000>,
|
||||
<0x44e10f90 0x40>;
|
||||
interrupts = <12 13 14>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
elm: elm@48080000 {
|
||||
compatible = "ti,816-elm";
|
||||
ti,hwmods = "elm";
|
||||
reg = <0x48080000 0x2000>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
gpio1: gpio@48032000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
ti,hwmods = "gpio1";
|
||||
reg = <0x48032000 0x1000>;
|
||||
interrupts = <97>;
|
||||
};
|
||||
|
||||
gpio2: gpio@4804c000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
ti,hwmods = "gpio2";
|
||||
reg = <0x4804c000 0x1000>;
|
||||
interrupts = <99>;
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
reg = <0x50000000 0x2000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <100>;
|
||||
gpmc,num-cs = <6>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
};
|
||||
|
||||
i2c1: i2c@48028000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
ti,hwmods = "i2c1";
|
||||
reg = <0x48028000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <70>;
|
||||
dmas = <&edma 58 &edma 59>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
i2c2: i2c@4802a000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
ti,hwmods = "i2c2";
|
||||
reg = <0x4802a000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <71>;
|
||||
dmas = <&edma 60 &edma 61>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@48200000 {
|
||||
compatible = "ti,dm816-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x48200000 0x1000>;
|
||||
};
|
||||
|
||||
mailbox: mailbox@480c8000 {
|
||||
compatible = "ti,omap4-mailbox";
|
||||
reg = <0x480c8000 0x2000>;
|
||||
interrupts = <77>;
|
||||
ti,hwmods = "mailbox";
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <12>;
|
||||
mbox_dsp: mbox_dsp {
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio: mdio@4a100800 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4a100800 0x100>;
|
||||
ti,hwmods = "davinci_mdio";
|
||||
bus_freq = <1000000>;
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@4a100000 {
|
||||
compatible = "ti,dm816-emac";
|
||||
ti,hwmods = "emac0";
|
||||
reg = <0x4a100000 0x800
|
||||
0x4a100900 0x3700>;
|
||||
clocks = <&sysclk24_ck>;
|
||||
ti,davinci-ctrl-reg-offset = <0>;
|
||||
ti,davinci-ctrl-mod-reg-offset = <0x900>;
|
||||
ti,davinci-ctrl-ram-offset = <0x2000>;
|
||||
ti,davinci-ctrl-ram-size = <0x2000>;
|
||||
interrupts = <40 41 42 43>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
eth1: ethernet@4a120000 {
|
||||
compatible = "ti,dm816-emac";
|
||||
ti,hwmods = "emac1";
|
||||
reg = <0x4a120000 0x4000>;
|
||||
clocks = <&sysclk24_ck>;
|
||||
ti,davinci-ctrl-reg-offset = <0>;
|
||||
ti,davinci-ctrl-mod-reg-offset = <0x900>;
|
||||
ti,davinci-ctrl-ram-offset = <0x2000>;
|
||||
ti,davinci-ctrl-ram-size = <0x2000>;
|
||||
interrupts = <44 45 46 47>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
mcspi1: spi@48030000 {
|
||||
compatible = "ti,omap4-mcspi";
|
||||
reg = <0x48030000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <65>;
|
||||
ti,spi-num-cs = <4>;
|
||||
ti,hwmods = "mcspi1";
|
||||
dmas = <&edma 16 &edma 17
|
||||
&edma 18 &edma 19>;
|
||||
dma-names = "tx0", "rx0", "tx1", "rx1";
|
||||
};
|
||||
|
||||
mmc1: mmc@48060000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x48060000 0x11000>;
|
||||
ti,hwmods = "mmc1";
|
||||
interrupts = <64>;
|
||||
dmas = <&edma 24 &edma 25>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
timer1: timer@4802e000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x4802e000 0x2000>;
|
||||
interrupts = <67>;
|
||||
ti,hwmods = "timer1";
|
||||
ti,timer-alwon;
|
||||
};
|
||||
|
||||
timer2: timer@48040000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x48040000 0x2000>;
|
||||
interrupts = <68>;
|
||||
ti,hwmods = "timer2";
|
||||
};
|
||||
|
||||
timer3: timer@48042000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x48042000 0x2000>;
|
||||
interrupts = <69>;
|
||||
ti,hwmods = "timer3";
|
||||
};
|
||||
|
||||
timer4: timer@48044000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x48044000 0x2000>;
|
||||
interrupts = <92>;
|
||||
ti,hwmods = "timer4";
|
||||
};
|
||||
|
||||
timer5: timer@48046000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x48046000 0x2000>;
|
||||
interrupts = <93>;
|
||||
ti,hwmods = "timer5";
|
||||
};
|
||||
|
||||
timer6: timer@48048000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x48048000 0x2000>;
|
||||
interrupts = <94>;
|
||||
ti,hwmods = "timer6";
|
||||
};
|
||||
|
||||
timer7: timer@4804a000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x4804a000 0x2000>;
|
||||
interrupts = <95>;
|
||||
ti,hwmods = "timer7";
|
||||
};
|
||||
|
||||
uart1: uart@48020000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart1";
|
||||
reg = <0x48020000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <72>;
|
||||
dmas = <&edma 26 &edma 27>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart2: uart@48022000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart2";
|
||||
reg = <0x48022000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <73>;
|
||||
dmas = <&edma 28 &edma 29>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart3: uart@48024000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart3";
|
||||
reg = <0x48024000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <74>;
|
||||
dmas = <&edma 30 &edma 31>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
/* NOTE: USB needs a transceiver driver for phys to work */
|
||||
usb: usb_otg_hs@47401000 {
|
||||
compatible = "ti,am33xx-usb";
|
||||
reg = <0x47401000 0x400000>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,hwmods = "usb_otg_hs";
|
||||
|
||||
usb0: usb@47401000 {
|
||||
compatible = "ti,musb-am33xx";
|
||||
reg = <0x47401400 0x400
|
||||
0x47401000 0x200>;
|
||||
reg-names = "mc", "control";
|
||||
interrupts = <18>;
|
||||
interrupt-names = "mc";
|
||||
dr_mode = "otg";
|
||||
mentor,multipoint = <1>;
|
||||
mentor,num-eps = <16>;
|
||||
mentor,ram-bits = <12>;
|
||||
mentor,power = <500>;
|
||||
};
|
||||
|
||||
usb1: usb@47401800 {
|
||||
compatible = "ti,musb-am33xx";
|
||||
status = "disabled";
|
||||
reg = <0x47401c00 0x400
|
||||
0x47401800 0x200>;
|
||||
reg-names = "mc", "control";
|
||||
interrupts = <19>;
|
||||
interrupt-names = "mc";
|
||||
dr_mode = "otg";
|
||||
mentor,multipoint = <1>;
|
||||
mentor,num-eps = <16>;
|
||||
mentor,ram-bits = <12>;
|
||||
mentor,power = <500>;
|
||||
};
|
||||
};
|
||||
|
||||
wd_timer2: wd_timer@480c2000 {
|
||||
compatible = "ti,omap3-wdt";
|
||||
ti,hwmods = "wd_timer";
|
||||
reg = <0x480c2000 0x1000>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "dm816x-clocks.dtsi"
|
||||
|
|
@ -121,6 +121,18 @@
|
|||
0x418 (MUX_MODE15) /* wakeup0.off */
|
||||
>;
|
||||
};
|
||||
|
||||
qspi1_pins: pinmux_qspi1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
|
||||
0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
|
||||
0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
|
||||
0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
|
||||
0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
|
||||
0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
|
||||
0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
|
|
@ -461,3 +473,68 @@
|
|||
pinctrl-0 = <&dcan1_pins_default>;
|
||||
pinctrl-1 = <&dcan1_pins_sleep>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qspi1_pins>;
|
||||
|
||||
spi-max-frequency = <48000000>;
|
||||
m25p80@0 {
|
||||
compatible = "s25fl256s1";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* MTD partition table.
|
||||
* The ROM checks the first four physical blocks
|
||||
* for a valid file to boot and the flash here is
|
||||
* 64KiB block size.
|
||||
*/
|
||||
partition@0 {
|
||||
label = "QSPI.SPL";
|
||||
reg = <0x00000000 0x000010000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "QSPI.SPL.backup1";
|
||||
reg = <0x00010000 0x00010000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "QSPI.SPL.backup2";
|
||||
reg = <0x00020000 0x00010000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "QSPI.SPL.backup3";
|
||||
reg = <0x00030000 0x00010000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "QSPI.u-boot";
|
||||
reg = <0x00040000 0x00100000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "QSPI.u-boot-spl-os";
|
||||
reg = <0x00140000 0x00080000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "QSPI.u-boot-env";
|
||||
reg = <0x001c0000 0x00010000>;
|
||||
};
|
||||
partition@7 {
|
||||
label = "QSPI.u-boot-env.backup1";
|
||||
reg = <0x001d0000 0x0010000>;
|
||||
};
|
||||
partition@8 {
|
||||
label = "QSPI.kernel";
|
||||
reg = <0x001e0000 0x0800000>;
|
||||
};
|
||||
partition@9 {
|
||||
label = "QSPI.file-system";
|
||||
reg = <0x009e0000 0x01620000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@
|
|||
#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
|
||||
#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
|
||||
#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
|
||||
#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
|
||||
#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
|
||||
#define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
|
||||
#define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
|
||||
|
|
|
|||
Loading…
Reference in New Issue