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drm/radeon: switch back to the CP ring for VM PT updates
For large VM page table updates, we can sometimes generate more packets than there is space on the ring. This happens more readily with the DMA ring since it is 64K (vs 1M for the CP). For now, switch back to the CP. For the next kernel, I have a patch to utilize IBs for VM PT updates which alleviates this problem. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=58354 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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fd5d93a001
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1 changed files with 3 additions and 3 deletions
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@ -1445,7 +1445,7 @@ static struct radeon_asic cayman_asic = {
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.vm = {
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.init = &cayman_vm_init,
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.fini = &cayman_vm_fini,
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.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
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.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.set_page = &cayman_vm_set_page,
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},
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.ring = {
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@ -1572,7 +1572,7 @@ static struct radeon_asic trinity_asic = {
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.vm = {
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.init = &cayman_vm_init,
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.fini = &cayman_vm_fini,
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.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
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.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.set_page = &cayman_vm_set_page,
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},
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.ring = {
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@ -1699,7 +1699,7 @@ static struct radeon_asic si_asic = {
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.vm = {
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.init = &si_vm_init,
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.fini = &si_vm_fini,
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.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
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.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.set_page = &si_vm_set_page,
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},
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.ring = {
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