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drm/i915/gen9: Add 2us read latency to WM level
According to the updated Bspec, The mailbox response data is not currently accounting for memory read latency. Add 2 microseconds to the result for each level. This patch adds 2us to latency of level 0 for all cases and for all other levels (1-7) only if latency[level] > 0. v2: Slightly rework the patch and add a big comment (Damien) v3: Rebase on top of the renames of the memory latency defines Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v1) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2) Reviewed-by: M, Satheeshakrishna <satheeshakrishna.m@intel.com> (v1) Cc: Lespiau, Damien <damien.lespiau@intel.com> Cc: M, Satheeshakrishna <satheeshakrishna.m@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -2286,6 +2286,7 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
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if (IS_GEN9(dev)) {
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uint32_t val;
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int ret;
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int level, max_level = ilk_wm_max_level(dev);
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/* read the first set of memory latencies[0:3] */
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val = 0; /* data0 to be programmed to 0 for first set */
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@ -2328,6 +2329,21 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
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wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK;
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/*
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* punit doesn't take into account the read latency so we need
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* to add 2us to the various latency levels we retrieve from
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* the punit.
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* - W0 is a bit special in that it's the only level that
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* can't be disabled if we want to have display working, so
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* we always add 2us there.
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* - For levels >=1, punit returns 0us latency when they are
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* disabled, so we respect that and don't add 2us then
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*/
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wm[0] += 2;
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for (level = 1; level <= max_level; level++)
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if (wm[level] != 0)
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wm[level] += 2;
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} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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uint64_t sskpd = I915_READ64(MCH_SSKPD);
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