dt-bindings: clock: imx8mp: Add ids for the audio shared gate

All these IDs are for one single HW gate (CCGR101) that is shared
between these root clocks.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/1667811007-19222-2-git-send-email-shengjiu.wang@nxp.com
This commit is contained in:
Abel Vesa 2022-11-07 16:50:06 +08:00 committed by Abel Vesa
parent 6a11d3a00d
commit 36759c4fe2

View file

@ -325,8 +325,17 @@
#define IMX8MP_CLK_CLKOUT2_DIV 318
#define IMX8MP_CLK_CLKOUT2 319
#define IMX8MP_CLK_USB_SUSP 320
#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT
#define IMX8MP_CLK_AUDIO_AXI_ROOT 321
#define IMX8MP_CLK_SAI1_ROOT 322
#define IMX8MP_CLK_SAI2_ROOT 323
#define IMX8MP_CLK_SAI3_ROOT 324
#define IMX8MP_CLK_SAI5_ROOT 325
#define IMX8MP_CLK_SAI6_ROOT 326
#define IMX8MP_CLK_SAI7_ROOT 327
#define IMX8MP_CLK_PDM_ROOT 328
#define IMX8MP_CLK_END 321
#define IMX8MP_CLK_END 329
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1