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ASoC: SOF: Intel: hda: Add definition for SDxFIFOS.FIFOS mask
The FIFOS (FIFO Size) field is in bit 0-15 of the register. Use the defined mask instead of a magic number for the FIFOS value masking in hda_dsp_stream_hw_params(). Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by: Chao Song <chao.song@linux.intel.com> Link: https://lore.kernel.org/r/20230915114018.1701-3-peter.ujfalusi@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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2 changed files with 4 additions and 1 deletions
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@ -668,7 +668,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
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snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
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sd_offset +
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SOF_HDA_ADSP_REG_SD_FIFOSIZE);
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hstream->fifo_size &= 0xffff;
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hstream->fifo_size &= SOF_HDA_SD_FIFOSIZE_FIFOS_MASK;
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hstream->fifo_size += 1;
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} else {
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hstream->fifo_size = 0;
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@ -135,6 +135,9 @@
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#define SOF_HDA_ADSP_REG_SD_BDLPU 0x1C
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#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
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/* SDxFIFOS FIFOS */
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#define SOF_HDA_SD_FIFOSIZE_FIFOS_MASK GENMASK(15, 0)
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/* CL: Software Position Based FIFO Capability Registers */
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#define SOF_DSP_REG_CL_SPBFIFO \
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(SOF_HDA_ADSP_LOADER_BASE + 0x20)
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