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ARM: zynq: DT: Add DDRC node
Add the DDR controller to the Zynq devicetree. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -146,6 +146,11 @@ L2: cache-controller {
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cache-level = <2>;
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cache-level = <2>;
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};
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};
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memory-controller@f8006000 {
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compatible = "xlnx,zynq-ddrc-a05";
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reg = <0xf8006000 0x1000>;
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} ;
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uart0: serial@e0000000 {
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uart0: serial@e0000000 {
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compatible = "xlnx,xuartps", "cdns,uart-r1p8";
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compatible = "xlnx,xuartps", "cdns,uart-r1p8";
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status = "disabled";
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status = "disabled";
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