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[MTD] [OneNAND] Add OMAP2 / OMAP3 OneNAND driver
This driver had resided in the OMAP tree but is now to be in MTD. Original authors were: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä IRQ and DMA support written by Timo Teras Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Adrian Hunter
David Woodhouse
parent
bb0eb217c9
commit
36cd4fb5d2
4 changed files with 791 additions and 1 deletions
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@ -27,6 +27,13 @@ config MTD_ONENAND_GENERIC
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help
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Support for OneNAND flash via platform device driver.
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config MTD_ONENAND_OMAP2
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tristate "OneNAND on OMAP2/OMAP3 support"
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depends on MTD_ONENAND && (ARCH_OMAP2 || ARCH_OMAP3)
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help
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Support for a OneNAND flash device connected to an OMAP2/OMAP3 CPU
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via the GPMC memory controller.
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config MTD_ONENAND_OTP
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bool "OneNAND OTP Support"
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select HAVE_MTD_OTP
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@ -7,6 +7,7 @@ obj-$(CONFIG_MTD_ONENAND) += onenand.o
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# Board specific.
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obj-$(CONFIG_MTD_ONENAND_GENERIC) += generic.o
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obj-$(CONFIG_MTD_ONENAND_OMAP2) += omap2.o
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# Simulator
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obj-$(CONFIG_MTD_ONENAND_SIM) += onenand_sim.o
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777
drivers/mtd/onenand/omap2.c
Normal file
777
drivers/mtd/onenand/omap2.c
Normal file
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@ -0,0 +1,777 @@
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/*
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* linux/drivers/mtd/onenand/omap2.c
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*
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* OneNAND driver for OMAP2 / OMAP3
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*
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* Copyright © 2005-2006 Nokia Corporation
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*
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* Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
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* IRQ and DMA support written by Timo Teras
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; see the file COPYING. If not, write to the Free Software
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* Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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*/
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/onenand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/mach/flash.h>
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#include <asm/arch/gpmc.h>
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#include <asm/arch/onenand.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/gpmc.h>
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#include <asm/arch/pm.h>
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#include <linux/dma-mapping.h>
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#include <asm/dma-mapping.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/board.h>
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#define DRIVER_NAME "omap2-onenand"
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#define ONENAND_IO_SIZE SZ_128K
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#define ONENAND_BUFRAM_SIZE (1024 * 5)
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struct omap2_onenand {
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struct platform_device *pdev;
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int gpmc_cs;
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unsigned long phys_base;
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int gpio_irq;
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struct mtd_info mtd;
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struct mtd_partition *parts;
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struct onenand_chip onenand;
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struct completion irq_done;
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struct completion dma_done;
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int dma_channel;
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int freq;
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int (*setup)(void __iomem *base, int freq);
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};
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static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
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{
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struct omap2_onenand *c = data;
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complete(&c->dma_done);
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}
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static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
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{
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struct omap2_onenand *c = dev_id;
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complete(&c->irq_done);
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return IRQ_HANDLED;
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}
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static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
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{
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return readw(c->onenand.base + reg);
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}
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static inline void write_reg(struct omap2_onenand *c, unsigned short value,
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int reg)
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{
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writew(value, c->onenand.base + reg);
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}
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static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
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{
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printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
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msg, state, ctrl, intr);
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}
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static void wait_warn(char *msg, int state, unsigned int ctrl,
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unsigned int intr)
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{
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printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
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"intr 0x%04x\n", msg, state, ctrl, intr);
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}
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static int omap2_onenand_wait(struct mtd_info *mtd, int state)
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{
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struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
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unsigned int intr = 0;
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unsigned int ctrl;
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unsigned long timeout;
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u32 syscfg;
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if (state == FL_RESETING) {
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int i;
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for (i = 0; i < 20; i++) {
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udelay(1);
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intr = read_reg(c, ONENAND_REG_INTERRUPT);
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if (intr & ONENAND_INT_MASTER)
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break;
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}
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ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
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if (ctrl & ONENAND_CTRL_ERROR) {
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wait_err("controller error", state, ctrl, intr);
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return -EIO;
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}
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if (!(intr & ONENAND_INT_RESET)) {
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wait_err("timeout", state, ctrl, intr);
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return -EIO;
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}
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return 0;
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}
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if (state != FL_READING) {
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int result;
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/* Turn interrupts on */
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syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
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syscfg |= ONENAND_SYS_CFG1_IOBE;
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write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
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INIT_COMPLETION(c->irq_done);
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if (c->gpio_irq) {
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result = omap_get_gpio_datain(c->gpio_irq);
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if (result == -1) {
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ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
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intr = read_reg(c, ONENAND_REG_INTERRUPT);
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wait_err("gpio error", state, ctrl, intr);
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return -EIO;
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}
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} else
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result = 0;
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if (result == 0) {
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int retry_cnt = 0;
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retry:
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result = wait_for_completion_timeout(&c->irq_done,
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msecs_to_jiffies(20));
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if (result == 0) {
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/* Timeout after 20ms */
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ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
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if (ctrl & ONENAND_CTRL_ONGO) {
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/*
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* The operation seems to be still going
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* so give it some more time.
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*/
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retry_cnt += 1;
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if (retry_cnt < 3)
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goto retry;
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intr = read_reg(c,
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ONENAND_REG_INTERRUPT);
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wait_err("timeout", state, ctrl, intr);
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return -EIO;
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}
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intr = read_reg(c, ONENAND_REG_INTERRUPT);
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if ((intr & ONENAND_INT_MASTER) == 0)
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wait_warn("timeout", state, ctrl, intr);
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}
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}
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} else {
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/* Turn interrupts off */
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syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
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syscfg &= ~ONENAND_SYS_CFG1_IOBE;
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write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
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timeout = jiffies + msecs_to_jiffies(20);
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while (time_before(jiffies, timeout)) {
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intr = read_reg(c, ONENAND_REG_INTERRUPT);
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if (intr & ONENAND_INT_MASTER)
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break;
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}
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}
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intr = read_reg(c, ONENAND_REG_INTERRUPT);
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ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
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if (intr & ONENAND_INT_READ) {
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int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
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if (ecc) {
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unsigned int addr1, addr8;
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addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
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addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
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if (ecc & ONENAND_ECC_2BIT_ALL) {
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printk(KERN_ERR "onenand_wait: ECC error = "
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"0x%04x, addr1 %#x, addr8 %#x\n",
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ecc, addr1, addr8);
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mtd->ecc_stats.failed++;
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return -EBADMSG;
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} else if (ecc & ONENAND_ECC_1BIT_ALL) {
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printk(KERN_NOTICE "onenand_wait: correctable "
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"ECC error = 0x%04x, addr1 %#x, "
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"addr8 %#x\n", ecc, addr1, addr8);
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mtd->ecc_stats.corrected++;
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}
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}
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} else if (state == FL_READING) {
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wait_err("timeout", state, ctrl, intr);
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return -EIO;
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}
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if (ctrl & ONENAND_CTRL_ERROR) {
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wait_err("controller error", state, ctrl, intr);
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if (ctrl & ONENAND_CTRL_LOCK)
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printk(KERN_ERR "onenand_wait: "
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"Device is write protected!!!\n");
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return -EIO;
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}
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if (ctrl & 0xFE9F)
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wait_warn("unexpected controller status", state, ctrl, intr);
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return 0;
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}
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static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
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{
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struct onenand_chip *this = mtd->priv;
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if (ONENAND_CURRENT_BUFFERRAM(this)) {
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if (area == ONENAND_DATARAM)
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return mtd->writesize;
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if (area == ONENAND_SPARERAM)
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return mtd->oobsize;
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}
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return 0;
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}
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#if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
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static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
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unsigned char *buffer, int offset,
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size_t count)
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{
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struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
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struct onenand_chip *this = mtd->priv;
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dma_addr_t dma_src, dma_dst;
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int bram_offset;
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unsigned long timeout;
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void *buf = (void *)buffer;
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size_t xtra;
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volatile unsigned *done;
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bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
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if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
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goto out_copy;
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if (buf >= high_memory) {
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struct page *p1;
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if (((size_t)buf & PAGE_MASK) !=
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((size_t)(buf + count - 1) & PAGE_MASK))
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goto out_copy;
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p1 = vmalloc_to_page(buf);
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if (!p1)
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goto out_copy;
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buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
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}
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xtra = count & 3;
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if (xtra) {
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count -= xtra;
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memcpy(buf + count, this->base + bram_offset + count, xtra);
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}
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dma_src = c->phys_base + bram_offset;
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dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
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if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
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dev_err(&c->pdev->dev,
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"Couldn't DMA map a %d byte buffer\n",
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count);
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goto out_copy;
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}
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omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
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count >> 2, 1, 0, 0, 0);
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omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
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dma_src, 0, 0);
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omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
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dma_dst, 0, 0);
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INIT_COMPLETION(c->dma_done);
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omap_start_dma(c->dma_channel);
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timeout = jiffies + msecs_to_jiffies(20);
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done = &c->dma_done.done;
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while (time_before(jiffies, timeout))
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if (*done)
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break;
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dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
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if (!*done) {
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dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
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goto out_copy;
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}
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return 0;
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out_copy:
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memcpy(buf, this->base + bram_offset, count);
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return 0;
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}
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static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
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const unsigned char *buffer,
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int offset, size_t count)
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{
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struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
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struct onenand_chip *this = mtd->priv;
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dma_addr_t dma_src, dma_dst;
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int bram_offset;
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unsigned long timeout;
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void *buf = (void *)buffer;
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volatile unsigned *done;
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bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
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if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
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goto out_copy;
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/* panic_write() may be in an interrupt context */
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if (in_interrupt())
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goto out_copy;
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if (buf >= high_memory) {
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struct page *p1;
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if (((size_t)buf & PAGE_MASK) !=
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((size_t)(buf + count - 1) & PAGE_MASK))
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goto out_copy;
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p1 = vmalloc_to_page(buf);
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if (!p1)
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goto out_copy;
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buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
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}
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dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
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dma_dst = c->phys_base + bram_offset;
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if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
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dev_err(&c->pdev->dev,
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"Couldn't DMA map a %d byte buffer\n",
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count);
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return -1;
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}
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omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
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count >> 2, 1, 0, 0, 0);
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omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
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dma_src, 0, 0);
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omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
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dma_dst, 0, 0);
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INIT_COMPLETION(c->dma_done);
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omap_start_dma(c->dma_channel);
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timeout = jiffies + msecs_to_jiffies(20);
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done = &c->dma_done.done;
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while (time_before(jiffies, timeout))
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if (*done)
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break;
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dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
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if (!*done) {
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dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
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goto out_copy;
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}
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return 0;
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out_copy:
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memcpy(this->base + bram_offset, buf, count);
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return 0;
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}
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#else
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int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
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unsigned char *buffer, int offset,
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size_t count);
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int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
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const unsigned char *buffer,
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int offset, size_t count);
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#endif
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#if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
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static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
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unsigned char *buffer, int offset,
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size_t count)
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{
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struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
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struct onenand_chip *this = mtd->priv;
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dma_addr_t dma_src, dma_dst;
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int bram_offset;
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|
||||
bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
|
||||
/* DMA is not used. Revisit PM requirements before enabling it. */
|
||||
if (1 || (c->dma_channel < 0) ||
|
||||
((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
|
||||
(((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
|
||||
memcpy(buffer, (__force void *)(this->base + bram_offset),
|
||||
count);
|
||||
return 0;
|
||||
}
|
||||
|
||||
dma_src = c->phys_base + bram_offset;
|
||||
dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
|
||||
DMA_FROM_DEVICE);
|
||||
if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
|
||||
dev_err(&c->pdev->dev,
|
||||
"Couldn't DMA map a %d byte buffer\n",
|
||||
count);
|
||||
return -1;
|
||||
}
|
||||
|
||||
omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
|
||||
count / 4, 1, 0, 0, 0);
|
||||
omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
|
||||
dma_src, 0, 0);
|
||||
omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
|
||||
dma_dst, 0, 0);
|
||||
|
||||
INIT_COMPLETION(c->dma_done);
|
||||
omap_start_dma(c->dma_channel);
|
||||
wait_for_completion(&c->dma_done);
|
||||
|
||||
dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
|
||||
const unsigned char *buffer,
|
||||
int offset, size_t count)
|
||||
{
|
||||
struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
|
||||
struct onenand_chip *this = mtd->priv;
|
||||
dma_addr_t dma_src, dma_dst;
|
||||
int bram_offset;
|
||||
|
||||
bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
|
||||
/* DMA is not used. Revisit PM requirements before enabling it. */
|
||||
if (1 || (c->dma_channel < 0) ||
|
||||
((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
|
||||
(((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
|
||||
memcpy((__force void *)(this->base + bram_offset), buffer,
|
||||
count);
|
||||
return 0;
|
||||
}
|
||||
|
||||
dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
|
||||
DMA_TO_DEVICE);
|
||||
dma_dst = c->phys_base + bram_offset;
|
||||
if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
|
||||
dev_err(&c->pdev->dev,
|
||||
"Couldn't DMA map a %d byte buffer\n",
|
||||
count);
|
||||
return -1;
|
||||
}
|
||||
|
||||
omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
|
||||
count / 2, 1, 0, 0, 0);
|
||||
omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
|
||||
dma_src, 0, 0);
|
||||
omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
|
||||
dma_dst, 0, 0);
|
||||
|
||||
INIT_COMPLETION(c->dma_done);
|
||||
omap_start_dma(c->dma_channel);
|
||||
wait_for_completion(&c->dma_done);
|
||||
|
||||
dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
|
||||
unsigned char *buffer, int offset,
|
||||
size_t count);
|
||||
|
||||
int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
|
||||
const unsigned char *buffer,
|
||||
int offset, size_t count);
|
||||
|
||||
#endif
|
||||
|
||||
static struct platform_driver omap2_onenand_driver;
|
||||
|
||||
static int __adjust_timing(struct device *dev, void *data)
|
||||
{
|
||||
int ret = 0;
|
||||
struct omap2_onenand *c;
|
||||
|
||||
c = dev_get_drvdata(dev);
|
||||
|
||||
BUG_ON(c->setup == NULL);
|
||||
|
||||
/* DMA is not in use so this is all that is needed */
|
||||
/* Revisit for OMAP3! */
|
||||
ret = c->setup(c->onenand.base, c->freq);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int omap2_onenand_rephase(void)
|
||||
{
|
||||
return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
|
||||
NULL, __adjust_timing);
|
||||
}
|
||||
|
||||
static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
/* With certain content in the buffer RAM, the OMAP boot ROM code
|
||||
* can recognize the flash chip incorrectly. Zero it out before
|
||||
* soft reset.
|
||||
*/
|
||||
memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
|
||||
}
|
||||
|
||||
static int __devinit omap2_onenand_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct omap_onenand_platform_data *pdata;
|
||||
struct omap2_onenand *c;
|
||||
int r;
|
||||
|
||||
pdata = pdev->dev.platform_data;
|
||||
if (pdata == NULL) {
|
||||
dev_err(&pdev->dev, "platform data missing\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
|
||||
if (!c)
|
||||
return -ENOMEM;
|
||||
|
||||
init_completion(&c->irq_done);
|
||||
init_completion(&c->dma_done);
|
||||
c->gpmc_cs = pdata->cs;
|
||||
c->gpio_irq = pdata->gpio_irq;
|
||||
c->dma_channel = pdata->dma_channel;
|
||||
if (c->dma_channel < 0) {
|
||||
/* if -1, don't use DMA */
|
||||
c->gpio_irq = 0;
|
||||
}
|
||||
|
||||
r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base);
|
||||
if (r < 0) {
|
||||
dev_err(&pdev->dev, "Cannot request GPMC CS\n");
|
||||
goto err_kfree;
|
||||
}
|
||||
|
||||
if (request_mem_region(c->phys_base, ONENAND_IO_SIZE,
|
||||
pdev->dev.driver->name) == NULL) {
|
||||
dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, "
|
||||
"size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE);
|
||||
r = -EBUSY;
|
||||
goto err_free_cs;
|
||||
}
|
||||
c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE);
|
||||
if (c->onenand.base == NULL) {
|
||||
r = -ENOMEM;
|
||||
goto err_release_mem_region;
|
||||
}
|
||||
|
||||
if (pdata->onenand_setup != NULL) {
|
||||
r = pdata->onenand_setup(c->onenand.base, c->freq);
|
||||
if (r < 0) {
|
||||
dev_err(&pdev->dev, "Onenand platform setup failed: "
|
||||
"%d\n", r);
|
||||
goto err_iounmap;
|
||||
}
|
||||
c->setup = pdata->onenand_setup;
|
||||
}
|
||||
|
||||
if (c->gpio_irq) {
|
||||
if ((r = omap_request_gpio(c->gpio_irq)) < 0) {
|
||||
dev_err(&pdev->dev, "Failed to request GPIO%d for "
|
||||
"OneNAND\n", c->gpio_irq);
|
||||
goto err_iounmap;
|
||||
}
|
||||
omap_set_gpio_direction(c->gpio_irq, 1);
|
||||
|
||||
if ((r = request_irq(OMAP_GPIO_IRQ(c->gpio_irq),
|
||||
omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
|
||||
pdev->dev.driver->name, c)) < 0)
|
||||
goto err_release_gpio;
|
||||
}
|
||||
|
||||
if (c->dma_channel >= 0) {
|
||||
r = omap_request_dma(0, pdev->dev.driver->name,
|
||||
omap2_onenand_dma_cb, (void *) c,
|
||||
&c->dma_channel);
|
||||
if (r == 0) {
|
||||
omap_set_dma_write_mode(c->dma_channel,
|
||||
OMAP_DMA_WRITE_NON_POSTED);
|
||||
omap_set_dma_src_data_pack(c->dma_channel, 1);
|
||||
omap_set_dma_src_burst_mode(c->dma_channel,
|
||||
OMAP_DMA_DATA_BURST_8);
|
||||
omap_set_dma_dest_data_pack(c->dma_channel, 1);
|
||||
omap_set_dma_dest_burst_mode(c->dma_channel,
|
||||
OMAP_DMA_DATA_BURST_8);
|
||||
} else {
|
||||
dev_info(&pdev->dev,
|
||||
"failed to allocate DMA for OneNAND, "
|
||||
"using PIO instead\n");
|
||||
c->dma_channel = -1;
|
||||
}
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
|
||||
"base %p\n", c->gpmc_cs, c->phys_base,
|
||||
c->onenand.base);
|
||||
|
||||
c->pdev = pdev;
|
||||
c->mtd.name = pdev->dev.bus_id;
|
||||
c->mtd.priv = &c->onenand;
|
||||
c->mtd.owner = THIS_MODULE;
|
||||
|
||||
if (c->dma_channel >= 0) {
|
||||
struct onenand_chip *this = &c->onenand;
|
||||
|
||||
this->wait = omap2_onenand_wait;
|
||||
if (cpu_is_omap34xx()) {
|
||||
this->read_bufferram = omap3_onenand_read_bufferram;
|
||||
this->write_bufferram = omap3_onenand_write_bufferram;
|
||||
} else {
|
||||
this->read_bufferram = omap2_onenand_read_bufferram;
|
||||
this->write_bufferram = omap2_onenand_write_bufferram;
|
||||
}
|
||||
}
|
||||
|
||||
if ((r = onenand_scan(&c->mtd, 1)) < 0)
|
||||
goto err_release_dma;
|
||||
|
||||
switch ((c->onenand.version_id >> 4) & 0xf) {
|
||||
case 0:
|
||||
c->freq = 40;
|
||||
break;
|
||||
case 1:
|
||||
c->freq = 54;
|
||||
break;
|
||||
case 2:
|
||||
c->freq = 66;
|
||||
break;
|
||||
case 3:
|
||||
c->freq = 83;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
if (pdata->parts != NULL)
|
||||
r = add_mtd_partitions(&c->mtd, pdata->parts,
|
||||
pdata->nr_parts);
|
||||
else
|
||||
#endif
|
||||
r = add_mtd_device(&c->mtd);
|
||||
if (r < 0)
|
||||
goto err_release_onenand;
|
||||
|
||||
platform_set_drvdata(pdev, c);
|
||||
|
||||
return 0;
|
||||
|
||||
err_release_onenand:
|
||||
onenand_release(&c->mtd);
|
||||
err_release_dma:
|
||||
if (c->dma_channel != -1)
|
||||
omap_free_dma(c->dma_channel);
|
||||
if (c->gpio_irq)
|
||||
free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
|
||||
err_release_gpio:
|
||||
if (c->gpio_irq)
|
||||
omap_free_gpio(c->gpio_irq);
|
||||
err_iounmap:
|
||||
iounmap(c->onenand.base);
|
||||
err_release_mem_region:
|
||||
release_mem_region(c->phys_base, ONENAND_IO_SIZE);
|
||||
err_free_cs:
|
||||
gpmc_cs_free(c->gpmc_cs);
|
||||
err_kfree:
|
||||
kfree(c);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int __devexit omap2_onenand_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
BUG_ON(c == NULL);
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
if (c->parts)
|
||||
del_mtd_partitions(&c->mtd);
|
||||
else
|
||||
del_mtd_device(&c->mtd);
|
||||
#else
|
||||
del_mtd_device(&c->mtd);
|
||||
#endif
|
||||
|
||||
onenand_release(&c->mtd);
|
||||
if (c->dma_channel != -1)
|
||||
omap_free_dma(c->dma_channel);
|
||||
omap2_onenand_shutdown(pdev);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
if (c->gpio_irq) {
|
||||
free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
|
||||
omap_free_gpio(c->gpio_irq);
|
||||
}
|
||||
iounmap(c->onenand.base);
|
||||
release_mem_region(c->phys_base, ONENAND_IO_SIZE);
|
||||
kfree(c);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver omap2_onenand_driver = {
|
||||
.probe = omap2_onenand_probe,
|
||||
.remove = omap2_onenand_remove,
|
||||
.shutdown = omap2_onenand_shutdown,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init omap2_onenand_init(void)
|
||||
{
|
||||
printk(KERN_INFO "OneNAND driver initializing\n");
|
||||
return platform_driver_register(&omap2_onenand_driver);
|
||||
}
|
||||
|
||||
static void __exit omap2_onenand_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&omap2_onenand_driver);
|
||||
}
|
||||
|
||||
module_init(omap2_onenand_init);
|
||||
module_exit(omap2_onenand_exit);
|
||||
|
||||
MODULE_ALIAS(DRIVER_NAME);
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
|
||||
MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");
|
||||
|
|
@ -16,6 +16,11 @@ struct omap_onenand_platform_data {
|
|||
int gpio_irq;
|
||||
struct mtd_partition *parts;
|
||||
int nr_parts;
|
||||
int (*onenand_setup)(void __iomem *);
|
||||
int (*onenand_setup)(void __iomem *, int freq);
|
||||
int dma_channel;
|
||||
};
|
||||
|
||||
int omap2_onenand_rephase(void);
|
||||
|
||||
#define ONENAND_MAX_PARTITIONS 8
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue