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media: imx-pxp: Introduce pxp_read() and pxp_write() wrappers
Add pxp_read() and pxp_write() functions to wrap readl() and writel() respectively. This can be useful for debugging register accesses. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
parent
8293b3ee24
commit
36e5c36240
1 changed files with 64 additions and 54 deletions
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@ -253,6 +253,16 @@ static struct pxp_q_data *get_q_data(struct pxp_ctx *ctx,
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return &ctx->q_data[V4L2_M2M_DST];
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return &ctx->q_data[V4L2_M2M_DST];
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}
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}
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static inline u32 pxp_read(struct pxp_dev *dev, u32 reg)
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{
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return readl(dev->mmio + reg);
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}
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static inline void pxp_write(struct pxp_dev *dev, u32 reg, u32 value)
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{
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writel(value, dev->mmio + reg);
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}
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static u32 pxp_v4l2_pix_fmt_to_ps_format(u32 v4l2_pix_fmt)
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static u32 pxp_v4l2_pix_fmt_to_ps_format(u32 v4l2_pix_fmt)
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{
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{
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switch (v4l2_pix_fmt) {
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switch (v4l2_pix_fmt) {
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@ -505,11 +515,11 @@ static void pxp_setup_csc(struct pxp_ctx *ctx)
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csc1_coef = csc1_coef_smpte240m_lim;
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csc1_coef = csc1_coef_smpte240m_lim;
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}
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}
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writel(csc1_coef[0], dev->mmio + HW_PXP_CSC1_COEF0);
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pxp_write(dev, HW_PXP_CSC1_COEF0, csc1_coef[0]);
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writel(csc1_coef[1], dev->mmio + HW_PXP_CSC1_COEF1);
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pxp_write(dev, HW_PXP_CSC1_COEF1, csc1_coef[1]);
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writel(csc1_coef[2], dev->mmio + HW_PXP_CSC1_COEF2);
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pxp_write(dev, HW_PXP_CSC1_COEF2, csc1_coef[2]);
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} else {
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} else {
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writel(BM_PXP_CSC1_COEF0_BYPASS, dev->mmio + HW_PXP_CSC1_COEF0);
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pxp_write(dev, HW_PXP_CSC1_COEF0, BM_PXP_CSC1_COEF0_BYPASS);
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}
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}
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if (!pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
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if (!pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
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@ -725,15 +735,15 @@ static void pxp_setup_csc(struct pxp_ctx *ctx)
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BP_PXP_CSC2_CTRL_CSC_MODE;
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BP_PXP_CSC2_CTRL_CSC_MODE;
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}
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}
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writel(csc2_ctrl, dev->mmio + HW_PXP_CSC2_CTRL);
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pxp_write(dev, HW_PXP_CSC2_CTRL, csc2_ctrl);
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writel(csc2_coef[0], dev->mmio + HW_PXP_CSC2_COEF0);
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pxp_write(dev, HW_PXP_CSC2_COEF0, csc2_coef[0]);
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writel(csc2_coef[1], dev->mmio + HW_PXP_CSC2_COEF1);
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pxp_write(dev, HW_PXP_CSC2_COEF1, csc2_coef[1]);
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writel(csc2_coef[2], dev->mmio + HW_PXP_CSC2_COEF2);
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pxp_write(dev, HW_PXP_CSC2_COEF2, csc2_coef[2]);
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writel(csc2_coef[3], dev->mmio + HW_PXP_CSC2_COEF3);
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pxp_write(dev, HW_PXP_CSC2_COEF3, csc2_coef[3]);
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writel(csc2_coef[4], dev->mmio + HW_PXP_CSC2_COEF4);
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pxp_write(dev, HW_PXP_CSC2_COEF4, csc2_coef[4]);
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writel(csc2_coef[5], dev->mmio + HW_PXP_CSC2_COEF5);
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pxp_write(dev, HW_PXP_CSC2_COEF5, csc2_coef[5]);
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} else {
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} else {
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writel(BM_PXP_CSC2_CTRL_BYPASS, dev->mmio + HW_PXP_CSC2_CTRL);
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pxp_write(dev, HW_PXP_CSC2_CTRL, BM_PXP_CSC2_CTRL_BYPASS);
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}
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}
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}
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}
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@ -810,8 +820,8 @@ static void pxp_set_data_path(struct pxp_ctx *ctx)
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ctrl1 |= BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(3);
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ctrl1 |= BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(3);
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ctrl1 |= BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(3);
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ctrl1 |= BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(3);
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writel(ctrl0, dev->mmio + HW_PXP_DATA_PATH_CTRL0);
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pxp_write(dev, HW_PXP_DATA_PATH_CTRL0, ctrl0);
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writel(ctrl1, dev->mmio + HW_PXP_DATA_PATH_CTRL1);
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pxp_write(dev, HW_PXP_DATA_PATH_CTRL1, ctrl1);
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}
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}
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static int pxp_start(struct pxp_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
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static int pxp_start(struct pxp_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
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@ -967,48 +977,48 @@ static int pxp_start(struct pxp_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
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BF_PXP_PS_SCALE_XSCALE(xscale);
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BF_PXP_PS_SCALE_XSCALE(xscale);
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ps_offset = BF_PXP_PS_OFFSET_YOFFSET(0) | BF_PXP_PS_OFFSET_XOFFSET(0);
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ps_offset = BF_PXP_PS_OFFSET_YOFFSET(0) | BF_PXP_PS_OFFSET_XOFFSET(0);
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writel(ctrl, dev->mmio + HW_PXP_CTRL);
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pxp_write(dev, HW_PXP_CTRL, ctrl);
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/* skip STAT */
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/* skip STAT */
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writel(out_ctrl, dev->mmio + HW_PXP_OUT_CTRL);
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pxp_write(dev, HW_PXP_OUT_CTRL, out_ctrl);
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writel(out_buf, dev->mmio + HW_PXP_OUT_BUF);
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pxp_write(dev, HW_PXP_OUT_BUF, out_buf);
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writel(out_buf2, dev->mmio + HW_PXP_OUT_BUF2);
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pxp_write(dev, HW_PXP_OUT_BUF2, out_buf2);
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writel(out_pitch, dev->mmio + HW_PXP_OUT_PITCH);
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pxp_write(dev, HW_PXP_OUT_PITCH, out_pitch);
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writel(out_lrc, dev->mmio + HW_PXP_OUT_LRC);
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pxp_write(dev, HW_PXP_OUT_LRC, out_lrc);
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writel(out_ps_ulc, dev->mmio + HW_PXP_OUT_PS_ULC);
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pxp_write(dev, HW_PXP_OUT_PS_ULC, out_ps_ulc);
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writel(out_ps_lrc, dev->mmio + HW_PXP_OUT_PS_LRC);
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pxp_write(dev, HW_PXP_OUT_PS_LRC, out_ps_lrc);
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writel(as_ulc, dev->mmio + HW_PXP_OUT_AS_ULC);
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pxp_write(dev, HW_PXP_OUT_AS_ULC, as_ulc);
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writel(as_lrc, dev->mmio + HW_PXP_OUT_AS_LRC);
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pxp_write(dev, HW_PXP_OUT_AS_LRC, as_lrc);
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writel(ps_ctrl, dev->mmio + HW_PXP_PS_CTRL);
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pxp_write(dev, HW_PXP_PS_CTRL, ps_ctrl);
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writel(ps_buf, dev->mmio + HW_PXP_PS_BUF);
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pxp_write(dev, HW_PXP_PS_BUF, ps_buf);
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writel(ps_ubuf, dev->mmio + HW_PXP_PS_UBUF);
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pxp_write(dev, HW_PXP_PS_UBUF, ps_ubuf);
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writel(ps_vbuf, dev->mmio + HW_PXP_PS_VBUF);
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pxp_write(dev, HW_PXP_PS_VBUF, ps_vbuf);
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writel(ps_pitch, dev->mmio + HW_PXP_PS_PITCH);
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pxp_write(dev, HW_PXP_PS_PITCH, ps_pitch);
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writel(0x00ffffff, dev->mmio + HW_PXP_PS_BACKGROUND_0);
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pxp_write(dev, HW_PXP_PS_BACKGROUND_0, 0x00ffffff);
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writel(ps_scale, dev->mmio + HW_PXP_PS_SCALE);
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pxp_write(dev, HW_PXP_PS_SCALE, ps_scale);
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writel(ps_offset, dev->mmio + HW_PXP_PS_OFFSET);
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pxp_write(dev, HW_PXP_PS_OFFSET, ps_offset);
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/* disable processed surface color keying */
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/* disable processed surface color keying */
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writel(0x00ffffff, dev->mmio + HW_PXP_PS_CLRKEYLOW_0);
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pxp_write(dev, HW_PXP_PS_CLRKEYLOW_0, 0x00ffffff);
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writel(0x00000000, dev->mmio + HW_PXP_PS_CLRKEYHIGH_0);
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pxp_write(dev, HW_PXP_PS_CLRKEYHIGH_0, 0x00000000);
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/* disable alpha surface color keying */
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/* disable alpha surface color keying */
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writel(0x00ffffff, dev->mmio + HW_PXP_AS_CLRKEYLOW_0);
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pxp_write(dev, HW_PXP_AS_CLRKEYLOW_0, 0x00ffffff);
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writel(0x00000000, dev->mmio + HW_PXP_AS_CLRKEYHIGH_0);
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pxp_write(dev, HW_PXP_AS_CLRKEYHIGH_0, 0x00000000);
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/* setup CSC */
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/* setup CSC */
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pxp_setup_csc(ctx);
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pxp_setup_csc(ctx);
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/* bypass LUT */
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/* bypass LUT */
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writel(BM_PXP_LUT_CTRL_BYPASS, dev->mmio + HW_PXP_LUT_CTRL);
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pxp_write(dev, HW_PXP_LUT_CTRL, BM_PXP_LUT_CTRL_BYPASS);
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pxp_set_data_path(ctx);
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pxp_set_data_path(ctx);
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writel(0xffff, dev->mmio + HW_PXP_IRQ_MASK);
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pxp_write(dev, HW_PXP_IRQ_MASK, 0xffff);
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/* ungate, enable PS/AS/OUT and PXP operation */
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/* ungate, enable PS/AS/OUT and PXP operation */
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writel(BM_PXP_CTRL_IRQ_ENABLE, dev->mmio + HW_PXP_CTRL_SET);
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pxp_write(dev, HW_PXP_CTRL_SET, BM_PXP_CTRL_IRQ_ENABLE);
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writel(BM_PXP_CTRL_ENABLE | BM_PXP_CTRL_ENABLE_CSC2 |
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pxp_write(dev, HW_PXP_CTRL_SET,
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BM_PXP_CTRL_ENABLE_ROTATE0 |
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BM_PXP_CTRL_ENABLE | BM_PXP_CTRL_ENABLE_CSC2 |
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BM_PXP_CTRL_ENABLE_PS_AS_OUT, dev->mmio + HW_PXP_CTRL_SET);
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BM_PXP_CTRL_ENABLE_ROTATE0 | BM_PXP_CTRL_ENABLE_PS_AS_OUT);
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return 0;
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return 0;
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}
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}
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@ -1081,23 +1091,23 @@ static irqreturn_t pxp_irq_handler(int irq, void *dev_id)
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struct pxp_dev *dev = dev_id;
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struct pxp_dev *dev = dev_id;
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u32 stat;
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u32 stat;
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stat = readl(dev->mmio + HW_PXP_STAT);
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stat = pxp_read(dev, HW_PXP_STAT);
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if (stat & BM_PXP_STAT_IRQ0) {
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if (stat & BM_PXP_STAT_IRQ0) {
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/* we expect x = 0, y = height, irq0 = 1 */
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/* we expect x = 0, y = height, irq0 = 1 */
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if (stat & ~(BM_PXP_STAT_BLOCKX | BM_PXP_STAT_BLOCKY |
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if (stat & ~(BM_PXP_STAT_BLOCKX | BM_PXP_STAT_BLOCKY |
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BM_PXP_STAT_IRQ0))
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BM_PXP_STAT_IRQ0))
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dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
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dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
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writel(BM_PXP_STAT_IRQ0, dev->mmio + HW_PXP_STAT_CLR);
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pxp_write(dev, HW_PXP_STAT_CLR, BM_PXP_STAT_IRQ0);
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pxp_job_finish(dev);
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pxp_job_finish(dev);
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} else {
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} else {
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u32 irq = readl(dev->mmio + HW_PXP_IRQ);
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u32 irq = pxp_read(dev, HW_PXP_IRQ);
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dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
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dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
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dprintk(dev, "%s: irq = 0x%08x\n", __func__, irq);
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dprintk(dev, "%s: irq = 0x%08x\n", __func__, irq);
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writel(irq, dev->mmio + HW_PXP_IRQ_CLR);
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pxp_write(dev, HW_PXP_IRQ_CLR, irq);
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}
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}
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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@ -1741,18 +1751,18 @@ static int pxp_soft_reset(struct pxp_dev *dev)
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int ret;
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int ret;
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u32 val;
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u32 val;
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writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
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pxp_write(dev, HW_PXP_CTRL_CLR, BM_PXP_CTRL_SFTRST);
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writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
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pxp_write(dev, HW_PXP_CTRL_CLR, BM_PXP_CTRL_CLKGATE);
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writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
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pxp_write(dev, HW_PXP_CTRL_SET, BM_PXP_CTRL_SFTRST);
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ret = readl_poll_timeout(dev->mmio + HW_PXP_CTRL, val,
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ret = readl_poll_timeout(dev->mmio + HW_PXP_CTRL, val,
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val & BM_PXP_CTRL_CLKGATE, 0, 100);
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val & BM_PXP_CTRL_CLKGATE, 0, 100);
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
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pxp_write(dev, HW_PXP_CTRL_CLR, BM_PXP_CTRL_SFTRST);
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writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
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pxp_write(dev, HW_PXP_CTRL_CLR, BM_PXP_CTRL_CLKGATE);
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return 0;
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return 0;
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}
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}
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@ -1805,7 +1815,7 @@ static int pxp_probe(struct platform_device *pdev)
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goto err_clk;
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goto err_clk;
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}
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}
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hw_version = readl(dev->mmio + HW_PXP_VERSION);
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hw_version = pxp_read(dev, HW_PXP_VERSION);
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dev_dbg(&pdev->dev, "PXP Version %u.%u\n",
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dev_dbg(&pdev->dev, "PXP Version %u.%u\n",
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PXP_VERSION_MAJOR(hw_version), PXP_VERSION_MINOR(hw_version));
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PXP_VERSION_MAJOR(hw_version), PXP_VERSION_MINOR(hw_version));
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@ -1883,8 +1893,8 @@ static int pxp_remove(struct platform_device *pdev)
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{
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{
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struct pxp_dev *dev = platform_get_drvdata(pdev);
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struct pxp_dev *dev = platform_get_drvdata(pdev);
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writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_SET);
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pxp_write(dev, HW_PXP_CTRL_SET, BM_PXP_CTRL_CLKGATE);
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writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
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pxp_write(dev, HW_PXP_CTRL_SET, BM_PXP_CTRL_SFTRST);
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clk_disable_unprepare(dev->clk);
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clk_disable_unprepare(dev->clk);
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