mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-10-04 08:08:54 +00:00
Code Issues Releases Wiki Activity

clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM

Browse source 
There are cases where not all CPG_MOD clocks should be assumed to support
PM. For example on the CRU block there is a particular sequence that needs
to be followed to initialize the CSI-2 D-PHY in which individual clocks
need to be turned ON/OFF, due to which Runtime PM support wasn't used by
the CRU CSI-2 driver.

This patch adds support to allow indicating if PM is not supported by the
CPG_MOD clocks. Two new members no_pm_mod_clks and num_no_pm_mod_clks are
added to struct rzg2l_cpg_info so that MOD clocks which do not support PM
can be passed by no_pm_mod_clks[] array and when the driver uses Runtime
PM support the clk ID is matched against the no_pm_mod_clks[] array to see
if the clk is needed to be included as part of Runtime PM.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221026014227.162121-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2022-10-26 02:42:26 +01:00 committed by Geert Uytterhoeven
parent c82009584e
commit 3702cff6d9
2 changed files with 28 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

39
drivers/clk/renesas/rzg2l-cpg.c
View file

@ -95,6 +95,7 @@ struct rzg2l_pll5_mux_dsi_div_param {
* @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @info: Pointer to platform data
* @genpd: PM domain
* @mux_dsi_div_params: pll5 mux and dsi div parameters
*/
struct rzg2l_cpg_priv {
@ -111,6 +112,8 @@ struct rzg2l_cpg_priv {
const struct rzg2l_cpg_info *info;
struct generic_pm_domain genpd;
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
};
@ -1223,22 +1226,31 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
return devm_reset_controller_register(priv->dev, &priv->rcdev);
}
static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec)
static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
const struct of_phandle_args *clkspec)
{
const struct rzg2l_cpg_info *info = priv->info;
unsigned int id;
unsigned int i;
if (clkspec->args_count != 2)
return false;
switch (clkspec->args[0]) {
case CPG_MOD:
return true;
default:
if (clkspec->args[0] != CPG_MOD)
return false;
id = clkspec->args[1] + info->num_total_core_clks;
for (i = 0; i < info->num_no_pm_mod_clks; i++) {
if (info->no_pm_mod_clks[i] == id)
return false;
}
return true;
}
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev)
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
{
struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
bool once = true;
@ -1248,7 +1260,7 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
&clkspec)) {
if (rzg2l_cpg_is_pm_clk(&clkspec)) {
if (rzg2l_cpg_is_pm_clk(priv, &clkspec)) {
if (once) {
once = false;
error = pm_clk_create(dev);
@ -1298,16 +1310,13 @@ static void rzg2l_cpg_genpd_remove(void *data)
pm_genpd_remove(data);
}
static int __init rzg2l_cpg_add_clk_domain(struct device *dev)
static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
struct device_node *np = dev->of_node;
struct generic_pm_domain *genpd;
struct generic_pm_domain *genpd = &priv->genpd;
int ret;
genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL);
if (!genpd)
return -ENOMEM;
genpd->name = np->name;
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
GENPD_FLAG_ACTIVE_WAKEUP;
@ -1377,7 +1386,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
if (error)
return error;
error = rzg2l_cpg_add_clk_domain(dev);
error = rzg2l_cpg_add_clk_domain(priv);
if (error)
return error;

4
drivers/clk/renesas/rzg2l-cpg.h
View file

@ -256,6 +256,10 @@ struct rzg2l_cpg_info {
unsigned int num_mod_clks;
unsigned int num_hw_mod_clks;
/* No PM Module Clocks */
const unsigned int *no_pm_mod_clks;
unsigned int num_no_pm_mod_clks;
/* Resets */
const struct rzg2l_reset *resets;
unsigned int num_resets;