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drm/msm/dpu: split interrupt address arrays
There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Fixes: c731461322 ("drm/msm: Add missing struct identifier")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549653/
Link: https://lore.kernel.org/r/20230727144543.1483630-3-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov
parent
c54b4c3519
commit
370891f0d9
2 changed files with 72 additions and 38 deletions
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@ -51,11 +51,9 @@ struct dpu_intr_reg {
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};
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/*
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* struct dpu_intr_reg - List of DPU interrupt registers
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*
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* When making changes be sure to sync with dpu_hw_intr_reg
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* dpu_intr_set_legacy - List of DPU interrupt registers for DPU <= 6.x
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*/
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static const struct dpu_intr_reg dpu_intr_set[] = {
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static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
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[MDP_SSPP_TOP0_INTR] = {
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INTR_CLEAR,
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INTR_EN,
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@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
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MDP_AD4_INTR_EN_OFF(1),
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MDP_AD4_INTR_STATUS_OFF(1),
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},
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[MDP_INTF0_7xxx_INTR] = {
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};
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/*
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* dpu_intr_set_7xxx - List of DPU interrupt registers for DPU >= 7.0
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*/
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static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
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[MDP_SSPP_TOP0_INTR] = {
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INTR_CLEAR,
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INTR_EN,
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INTR_STATUS
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},
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[MDP_SSPP_TOP0_INTR2] = {
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INTR2_CLEAR,
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INTR2_EN,
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INTR2_STATUS
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},
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[MDP_SSPP_TOP0_HIST_INTR] = {
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HIST_INTR_CLEAR,
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HIST_INTR_EN,
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HIST_INTR_STATUS
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},
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[MDP_INTF0_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(0),
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MDP_INTF_REV_7xxx_INTR_EN(0),
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MDP_INTF_REV_7xxx_INTR_STATUS(0)
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},
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[MDP_INTF1_7xxx_INTR] = {
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[MDP_INTF1_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(1),
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MDP_INTF_REV_7xxx_INTR_EN(1),
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MDP_INTF_REV_7xxx_INTR_STATUS(1)
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},
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[MDP_INTF1_7xxx_TEAR_INTR] = {
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[MDP_INTF1_TEAR_INTR] = {
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MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
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MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
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MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
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},
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[MDP_INTF2_7xxx_INTR] = {
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[MDP_INTF2_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(2),
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MDP_INTF_REV_7xxx_INTR_EN(2),
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MDP_INTF_REV_7xxx_INTR_STATUS(2)
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},
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[MDP_INTF2_7xxx_TEAR_INTR] = {
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[MDP_INTF2_TEAR_INTR] = {
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MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
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MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
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MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
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},
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[MDP_INTF3_7xxx_INTR] = {
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[MDP_INTF3_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(3),
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MDP_INTF_REV_7xxx_INTR_EN(3),
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MDP_INTF_REV_7xxx_INTR_STATUS(3)
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},
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[MDP_INTF4_7xxx_INTR] = {
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[MDP_INTF4_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(4),
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MDP_INTF_REV_7xxx_INTR_EN(4),
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MDP_INTF_REV_7xxx_INTR_STATUS(4)
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},
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[MDP_INTF5_7xxx_INTR] = {
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[MDP_INTF5_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(5),
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MDP_INTF_REV_7xxx_INTR_EN(5),
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MDP_INTF_REV_7xxx_INTR_STATUS(5)
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},
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[MDP_INTF6_7xxx_INTR] = {
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[MDP_INTF6_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(6),
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MDP_INTF_REV_7xxx_INTR_EN(6),
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MDP_INTF_REV_7xxx_INTR_STATUS(6)
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},
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[MDP_INTF7_7xxx_INTR] = {
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[MDP_INTF7_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(7),
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MDP_INTF_REV_7xxx_INTR_EN(7),
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MDP_INTF_REV_7xxx_INTR_STATUS(7)
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},
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[MDP_INTF8_7xxx_INTR] = {
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[MDP_INTF8_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(8),
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MDP_INTF_REV_7xxx_INTR_EN(8),
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MDP_INTF_REV_7xxx_INTR_STATUS(8)
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@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
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return IRQ_NONE;
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spin_lock_irqsave(&intr->irq_lock, irq_flags);
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for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
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for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
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if (!test_bit(reg_idx, &intr->irq_mask))
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continue;
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/* Read interrupt status */
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irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
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irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
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/* Read enable mask */
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enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
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enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
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/* and clear the interrupt */
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if (irq_status)
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DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
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DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
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irq_status);
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/* Finally update IRQ status based on enable mask */
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@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
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assert_spin_locked(&intr->irq_lock);
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reg_idx = DPU_IRQ_REG(irq_idx);
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reg = &dpu_intr_set[reg_idx];
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reg = &intr->intr_set[reg_idx];
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/* Is this interrupt register supported on the platform */
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if (WARN_ON(!reg->en_off))
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return -EINVAL;
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cache_irq_mask = intr->cache_irq_mask[reg_idx];
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if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
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@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
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assert_spin_locked(&intr->irq_lock);
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reg_idx = DPU_IRQ_REG(irq_idx);
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reg = &dpu_intr_set[reg_idx];
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reg = &intr->intr_set[reg_idx];
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cache_irq_mask = intr->cache_irq_mask[reg_idx];
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if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
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@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
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if (!intr)
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return;
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for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
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for (i = 0; i < MDP_INTR_MAX; i++) {
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if (test_bit(i, &intr->irq_mask))
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DPU_REG_WRITE(&intr->hw,
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dpu_intr_set[i].clr_off, 0xffffffff);
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intr->intr_set[i].clr_off, 0xffffffff);
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}
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/* ensure register writes go through */
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@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
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if (!intr)
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return;
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for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
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for (i = 0; i < MDP_INTR_MAX; i++) {
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if (test_bit(i, &intr->irq_mask))
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DPU_REG_WRITE(&intr->hw,
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dpu_intr_set[i].en_off, 0x00000000);
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intr->intr_set[i].en_off, 0x00000000);
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}
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/* ensure register writes go through */
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@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
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reg_idx = DPU_IRQ_REG(irq_idx);
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intr_status = DPU_REG_READ(&intr->hw,
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dpu_intr_set[reg_idx].status_off) &
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intr->intr_set[reg_idx].status_off) &
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DPU_IRQ_MASK(irq_idx);
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if (intr_status)
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DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
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DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
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intr_status);
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/* ensure register writes go through */
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@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
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if (!intr)
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return ERR_PTR(-ENOMEM);
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if (m->mdss_ver->core_major_ver >= 7)
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intr->intr_set = dpu_intr_set_7xxx;
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else
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intr->intr_set = dpu_intr_set_legacy;
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intr->hw.blk_addr = addr + m->mdp[0].base;
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intr->total_irqs = nirq;
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@ -23,24 +23,29 @@ enum dpu_hw_intr_reg {
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MDP_INTF3_INTR,
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MDP_INTF4_INTR,
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MDP_INTF5_INTR,
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MDP_INTF6_INTR,
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MDP_INTF7_INTR,
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MDP_INTF8_INTR,
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MDP_INTF1_TEAR_INTR,
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MDP_INTF2_TEAR_INTR,
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MDP_AD4_0_INTR,
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MDP_AD4_1_INTR,
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MDP_INTF0_7xxx_INTR,
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MDP_INTF1_7xxx_INTR,
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MDP_INTF1_7xxx_TEAR_INTR,
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MDP_INTF2_7xxx_INTR,
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MDP_INTF2_7xxx_TEAR_INTR,
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MDP_INTF3_7xxx_INTR,
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MDP_INTF4_7xxx_INTR,
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MDP_INTF5_7xxx_INTR,
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MDP_INTF6_7xxx_INTR,
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MDP_INTF7_7xxx_INTR,
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MDP_INTF8_7xxx_INTR,
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MDP_INTR_MAX,
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};
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/* compatibility */
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#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
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#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
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#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
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#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
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#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
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#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
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#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
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#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
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#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
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#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
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#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
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#define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset)
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/**
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@ -60,6 +65,7 @@ struct dpu_hw_intr {
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u32 total_irqs;
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spinlock_t irq_lock;
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unsigned long irq_mask;
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const struct dpu_intr_reg *intr_set;
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struct {
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void (*cb)(void *arg, int irq_idx);
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