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drm/i915/reg: stop using implicit dev_priv in DSPCLK_GATE_D
Remove the implicit dev_priv usage in DSPCLK_GATE_D register, and pass it as parameter. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/41ca83573ca2d94bea568058f8cb8c35e814f8b1.1661855191.git.jani.nikula@intel.com
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parent
6d737d9bff
commit
3721d4fb76
6 changed files with 13 additions and 13 deletions
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@ -1157,10 +1157,10 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
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* (and never recovering) in this case. intel_dsi_post_disable() will
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* clear it when we turn off the display.
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*/
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val = intel_de_read(dev_priv, DSPCLK_GATE_D);
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val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
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val &= DPOUNIT_CLOCK_GATE_DISABLE;
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val |= VRHUNIT_CLOCK_GATE_DISABLE;
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intel_de_write(dev_priv, DSPCLK_GATE_D, val);
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intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
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/*
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* Disable trickle feed and enable pnd deadline calculation
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@ -183,12 +183,12 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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u32 val;
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
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val = intel_de_read(dev_priv, DSPCLK_GATE_D);
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val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
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if (!enable)
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val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
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else
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val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
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intel_de_write(dev_priv, DSPCLK_GATE_D, val);
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intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
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}
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static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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@ -211,9 +211,9 @@ static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
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/* WA_OVERLAY_CLKGATE:alm */
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if (enable)
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intel_de_write(dev_priv, DSPCLK_GATE_D, 0);
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intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), 0);
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else
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intel_de_write(dev_priv, DSPCLK_GATE_D,
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intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv),
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OVRUNIT_CLOCK_GATE_DISABLE);
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/* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
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@ -822,9 +822,9 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
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u32 val;
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/* Disable DPOunit clock gating, can stall pipe */
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val = intel_de_read(dev_priv, DSPCLK_GATE_D);
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val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
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val |= DPOUNIT_CLOCK_GATE_DISABLE;
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intel_de_write(dev_priv, DSPCLK_GATE_D, val);
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intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
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}
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if (!IS_GEMINILAKE(dev_priv))
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@ -998,9 +998,9 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state,
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vlv_dsi_pll_disable(encoder);
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val = intel_de_read(dev_priv, DSPCLK_GATE_D);
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val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
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val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
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intel_de_write(dev_priv, DSPCLK_GATE_D, val);
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intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
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}
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/* Assert reset */
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@ -1637,7 +1637,7 @@
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#define DSTATE_PLL_D3_OFF (1 << 3)
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#define DSTATE_GFX_CLOCK_GATING (1 << 1)
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#define DSTATE_DOT_CLOCK_GATING (1 << 0)
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#define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
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#define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
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# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
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# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
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# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
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@ -7994,7 +7994,7 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
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OVCUNIT_CLOCK_GATE_DISABLE;
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if (IS_GM45(dev_priv))
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dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
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intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D, dspclk_gate);
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intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D(dev_priv), dspclk_gate);
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g4x_disable_trickle_feed(dev_priv);
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}
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@ -8005,7 +8005,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
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intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
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intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
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intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
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intel_uncore_write(uncore, DSPCLK_GATE_D(dev_priv), 0);
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intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
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intel_uncore_write16(uncore, DEUC, 0);
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intel_uncore_write(uncore,
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