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drm/amdgpu: move PD/PT address calculation into backend function
This way we can better handle the differences for CPU based updates. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
132f34e4b5
commit
373ac645c9
1 changed files with 29 additions and 50 deletions
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@ -75,7 +75,8 @@ struct amdgpu_pte_update_params {
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/* indirect buffer to fill with commands */
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struct amdgpu_ib *ib;
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/* Function which actually does the update */
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void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe,
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void (*func)(struct amdgpu_pte_update_params *params,
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struct amdgpu_bo *bo, uint64_t pe,
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uint64_t addr, unsigned count, uint32_t incr,
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uint64_t flags);
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/* The next two are used during VM update by CPU
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@ -578,6 +579,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
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* amdgpu_vm_do_set_ptes - helper to call the right asic function
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*
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* @params: see amdgpu_pte_update_params definition
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* @bo: PD/PT to update
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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@ -588,10 +590,12 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
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* to setup the page table using the DMA.
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*/
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static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
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struct amdgpu_bo *bo,
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uint64_t pe, uint64_t addr,
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unsigned count, uint32_t incr,
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uint64_t flags)
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{
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pe += amdgpu_bo_gpu_offset(bo);
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trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
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if (count < 3) {
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@ -608,6 +612,7 @@ static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
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* amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
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*
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* @params: see amdgpu_pte_update_params definition
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* @bo: PD/PT to update
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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@ -617,13 +622,14 @@ static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
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* Traces the parameters and calls the DMA function to copy the PTEs.
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*/
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static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
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struct amdgpu_bo *bo,
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uint64_t pe, uint64_t addr,
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unsigned count, uint32_t incr,
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uint64_t flags)
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{
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uint64_t src = (params->src + (addr >> 12) * 8);
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pe += amdgpu_bo_gpu_offset(bo);
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trace_amdgpu_vm_copy_ptes(pe, src, count);
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amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
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@ -657,6 +663,7 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
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* amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
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*
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* @params: see amdgpu_pte_update_params definition
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* @bo: PD/PT to update
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* @pe: kmap addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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@ -666,6 +673,7 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
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* Write count number of PT/PD entries directly.
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*/
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static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
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struct amdgpu_bo *bo,
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uint64_t pe, uint64_t addr,
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unsigned count, uint32_t incr,
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uint64_t flags)
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@ -673,6 +681,8 @@ static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
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unsigned int i;
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uint64_t value;
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pe += (unsigned long)amdgpu_bo_kptr(bo);
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trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
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for (i = 0; i < count; i++) {
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@ -714,8 +724,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
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struct amdgpu_vm_pt *parent,
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struct amdgpu_vm_pt *entry)
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{
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struct amdgpu_bo *bo = entry->base.bo, *shadow = NULL, *pbo;
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uint64_t pd_addr, shadow_addr = 0;
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struct amdgpu_bo *bo = parent->base.bo, *pbo;
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uint64_t pde, pt, flags;
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unsigned level;
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@ -723,29 +732,17 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
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if (entry->huge)
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return;
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if (vm->use_cpu_for_update) {
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pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
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} else {
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pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
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shadow = parent->base.bo->shadow;
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if (shadow)
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shadow_addr = amdgpu_bo_gpu_offset(shadow);
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}
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for (level = 0, pbo = parent->base.bo->parent; pbo; ++level)
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for (level = 0, pbo = bo->parent; pbo; ++level)
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pbo = pbo->parent;
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level += params->adev->vm_manager.root_level;
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pt = amdgpu_bo_gpu_offset(bo);
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pt = amdgpu_bo_gpu_offset(entry->base.bo);
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flags = AMDGPU_PTE_VALID;
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amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
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if (shadow) {
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pde = shadow_addr + (entry - parent->entries) * 8;
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params->func(params, pde, pt, 1, 0, flags);
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}
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pde = pd_addr + (entry - parent->entries) * 8;
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params->func(params, pde, pt, 1, 0, flags);
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pde = (entry - parent->entries) * 8;
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if (bo->shadow)
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params->func(params, bo->shadow, pde, pt, 1, 0, flags);
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params->func(params, bo, pde, pt, 1, 0, flags);
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}
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/*
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@ -946,7 +943,7 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
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unsigned nptes, uint64_t dst,
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uint64_t flags)
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{
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uint64_t pd_addr, pde;
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uint64_t pde;
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/* In the case of a mixed PT the PDE must point to it*/
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if (p->adev->asic_type >= CHIP_VEGA10 && !p->src &&
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@ -969,18 +966,10 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
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entry->huge = true;
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amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags);
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if (p->func == amdgpu_vm_cpu_set_ptes) {
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pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
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} else {
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if (parent->base.bo->shadow) {
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pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
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pde = pd_addr + (entry - parent->entries) * 8;
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p->func(p, pde, dst, 1, 0, flags);
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}
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pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
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}
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pde = pd_addr + (entry - parent->entries) * 8;
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p->func(p, pde, dst, 1, 0, flags);
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pde = (entry - parent->entries) * 8;
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if (parent->base.bo->shadow)
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p->func(p, parent->base.bo->shadow, pde, dst, 1, 0, flags);
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p->func(p, parent->base.bo, pde, dst, 1, 0, flags);
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}
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/**
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@ -1006,7 +995,6 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
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uint64_t addr, pe_start;
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struct amdgpu_bo *pt;
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unsigned nptes;
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bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes);
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/* walk over the address space and update the page tables */
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for (addr = start; addr < end; addr += nptes,
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@ -1029,20 +1017,11 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
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continue;
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pt = entry->base.bo;
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if (use_cpu_update) {
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pe_start = (unsigned long)amdgpu_bo_kptr(pt);
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} else {
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if (pt->shadow) {
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pe_start = amdgpu_bo_gpu_offset(pt->shadow);
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pe_start += (addr & mask) * 8;
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params->func(params, pe_start, dst, nptes,
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AMDGPU_GPU_PAGE_SIZE, flags);
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}
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pe_start = amdgpu_bo_gpu_offset(pt);
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}
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pe_start += (addr & mask) * 8;
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params->func(params, pe_start, dst, nptes,
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pe_start = (addr & mask) * 8;
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if (pt->shadow)
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params->func(params, pt->shadow, pe_start, dst, nptes,
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AMDGPU_GPU_PAGE_SIZE, flags);
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params->func(params, pt, pe_start, dst, nptes,
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AMDGPU_GPU_PAGE_SIZE, flags);
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}
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