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net: stmmac: dwmac-meson8b: only configure the clocks in RGMII mode
Neither the m25_div_clk nor the m250_div_clk or m250_mux_clk are used in
RMII mode. The m25_div_clk output is routed to the RGMII PHY's "RGMII
clock".
This means that we don't need to configure the clocks in RMII mode. The
driver however did this - with no effect since the clocks are not routed
to the PHY in RMII mode.
While here also rename meson8b_init_clk to meson8b_init_rgmii_tx_clk to
make it easier to understand the code.
Fixes: 566e825162
("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
416ef9b15c
commit
37512b42f0
1 changed files with 21 additions and 25 deletions
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@ -81,7 +81,7 @@ static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
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writel(data, dwmac->regs + reg);
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}
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static int meson8b_init_clk(struct meson8b_dwmac *dwmac)
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static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
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{
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struct clk_init_data init;
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int i, ret;
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@ -176,7 +176,6 @@ static int meson8b_init_clk(struct meson8b_dwmac *dwmac)
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static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
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{
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int ret;
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unsigned long clk_rate;
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u8 tx_dly_val = 0;
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switch (dwmac->phy_mode) {
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@ -191,9 +190,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* Generate a 25MHz clock for the PHY */
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clk_rate = 25 * 1000 * 1000;
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/* enable RGMII mode */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
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PRG_ETH0_RGMII_MODE);
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@ -204,12 +200,24 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
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tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
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ret = clk_prepare_enable(dwmac->m25_div_clk);
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if (ret) {
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dev_err(&dwmac->pdev->dev, "failed to enable the PHY clock\n");
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return ret;
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}
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/* Generate the 25MHz RGMII clock for the PHY */
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ret = clk_set_rate(dwmac->m25_div_clk, 25 * 1000 * 1000);
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if (ret) {
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clk_disable_unprepare(dwmac->m25_div_clk);
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dev_err(&dwmac->pdev->dev, "failed to set PHY clock\n");
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return ret;
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}
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* Use the rate of the mux clock for the internal RMII PHY */
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clk_rate = clk_get_rate(dwmac->m250_mux_clk);
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/* disable RGMII mode -> enables RMII mode */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
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0);
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@ -231,20 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
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return -EINVAL;
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}
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ret = clk_prepare_enable(dwmac->m25_div_clk);
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if (ret) {
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dev_err(&dwmac->pdev->dev, "failed to enable the PHY clock\n");
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return ret;
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}
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ret = clk_set_rate(dwmac->m25_div_clk, clk_rate);
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if (ret) {
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clk_disable_unprepare(dwmac->m25_div_clk);
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dev_err(&dwmac->pdev->dev, "failed to set PHY clock\n");
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return ret;
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}
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/* enable TX_CLK and PHY_REF_CLK generator */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
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PRG_ETH0_TX_AND_PHY_REF_CLK);
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@ -294,7 +288,7 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
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&dwmac->tx_delay_ns))
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dwmac->tx_delay_ns = 2;
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ret = meson8b_init_clk(dwmac);
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ret = meson8b_init_rgmii_tx_clk(dwmac);
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if (ret)
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goto err_remove_config_dt;
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@ -311,7 +305,8 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
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return 0;
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err_clk_disable:
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clk_disable_unprepare(dwmac->m25_div_clk);
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if (phy_interface_mode_is_rgmii(dwmac->phy_mode))
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clk_disable_unprepare(dwmac->m25_div_clk);
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err_remove_config_dt:
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stmmac_remove_config_dt(pdev, plat_dat);
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@ -322,7 +317,8 @@ static int meson8b_dwmac_remove(struct platform_device *pdev)
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{
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struct meson8b_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev);
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clk_disable_unprepare(dwmac->m25_div_clk);
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if (phy_interface_mode_is_rgmii(dwmac->phy_mode))
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clk_disable_unprepare(dwmac->m25_div_clk);
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return stmmac_pltfr_remove(pdev);
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}
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