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SoCFPGA DTS updates for v5.5

Browse source 
- Arria10
 	- modify QSPI read-delay property
 - Agilex
 	- Add QSPI support
 	- Enable USB and LEDs
 	- Add service layer, fpga manager support
 - Stratix10
 	- Update QSPI reg address
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Merge tag 'socfpga_dts_updates_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt

SoCFPGA DTS updates for v5.5
- Arria10
	- modify QSPI read-delay property
- Agilex
	- Add QSPI support
	- Enable USB and LEDs
	- Add service layer, fpga manager support
- Stratix10
	- Update QSPI reg address

* tag 'socfpga_dts_updates_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: agilex: add service layer, fpga manager and fpga region
  arm64: agilex: enable USB and LEDs on agilex devkit
  arm64: dts: altera: update QSPI reg addresses for Stratix10
  arm64: dts: agilex: add QSPI support for Intel Agilex
  ARM: dts: arria10: Modify QSPI read_delay for Arria10

Link: https://lore.kernel.org/r/20191029143737.24850-1-dinguyen@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-11-02 13:34:24 -07:00
commit 3760828a8b
4 changed files with 93 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
View file

@ -19,7 +19,7 @@ flash0: n25q00@0 {
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,read-delay = <3>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;

4
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
View file

@ -178,12 +178,12 @@ partitions {
qspi_boot: partition@0 {
label = "Boot and fpga data";
reg = <0x0 0x4000000>;
reg = <0x0 0x034B0000>;
};
qspi_rootfs: partition@4000000 {
label = "Root Filesystem - JFFS2";
reg = <0x4000000 0x4000000>;
reg = <0x034B0000 0x0EB50000>;
};
};
};

32
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View file

@ -12,6 +12,19 @@ / {
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
service_reserved: svcbuffer@0 {
compatible = "shared-dma-pool";
reg = <0x0 0x0 0x0 0x1000000>;
alignment = <0x1000>;
no-map;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -81,6 +94,13 @@ soc {
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
base_fpga_region {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fpga-region";
fpga-mgr = <&fpga_mgr>;
};
gmac0: ethernet@ff800000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff800000 0x2000>;
@ -442,5 +462,17 @@ qspi: spi@ff8d2000 {
status = "disabled";
};
firmware {
svc {
compatible = "intel,stratix10-svc";
method = "smc";
memory-region = <&service_reserved>;
fpga_mgr: fpga-mgr {
compatible = "intel,stratix10-soc-fpga-mgr";
};
};
};
};
};

58
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
View file

@ -18,6 +18,24 @@ chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
hps0 {
label = "hps_led0";
gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
};
hps1 {
label = "hps_led1";
gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
};
hps2 {
label = "hps_led2";
gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
};
};
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
@ -70,6 +88,46 @@ &uart0 {
status = "okay";
};
&usb0 {
status = "okay";
disable-over-current;
};
&watchdog0 {
status = "okay";
};
&qspi {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mt25qu02g";
reg = <0>;
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <1>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
qspi_boot: partition@0 {
label = "Boot and fpga data";
reg = <0x0 0x034B0000>;
};
qspi_rootfs: partition@34B0000 {
label = "Root Filesystem - JFFS2";
reg = <0x034B0000 0x0EB50000>;
};
};
};
};