pwm: sti: Add new driver for ST's PWM IP
This driver supports all current STi platforms' PWM IPs. Signed-off-by: Ajit Pal Singh <ajitpal.singh@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> [thierry.reding: rename module to pwm-sti, fix build breakage] Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Lee Jones
Thierry Reding
parent
31c4fa3442
commit
378fe115d1
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@ -233,6 +233,16 @@ config PWM_SPEAR
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To compile this driver as a module, choose M here: the module
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will be called pwm-spear.
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config PWM_STI
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tristate "STiH4xx PWM support"
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depends on ARCH_STI
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depends on OF
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help
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Generic PWM framework driver for STiH4xx SoCs.
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To compile this driver as a module, choose M here: the module
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will be called pwm-sti.
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config PWM_TEGRA
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tristate "NVIDIA Tegra PWM support"
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depends on ARCH_TEGRA
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@ -21,6 +21,7 @@ obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
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obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
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obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
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obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
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obj-$(CONFIG_PWM_STI) += pwm-sti.o
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obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
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obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
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obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o
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@ -0,0 +1,366 @@
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/*
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* PWM device driver for ST SoCs.
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* Author: Ajit Pal Singh <ajitpal.singh@st.com>
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*
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* Copyright (C) 2013-2014 STMicroelectronics (R&D) Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/bsearch.h>
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#include <linux/clk.h>
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#include <linux/math64.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/time.h>
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#define STI_DS_REG(ch) (4 * (ch)) /* Channel's Duty Cycle register */
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#define STI_PWMCR 0x50 /* Control/Config register */
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#define STI_INTEN 0x54 /* Interrupt Enable/Disable register */
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/* Regfield IDs */
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enum {
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PWMCLK_PRESCALE,
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PWM_EN,
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PWM_INT_EN,
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/* Keep last */
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MAX_REGFIELDS
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};
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struct sti_pwm_compat_data {
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const struct reg_field *reg_fields;
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unsigned int num_chan;
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unsigned int max_pwm_cnt;
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unsigned int max_prescale;
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};
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struct sti_pwm_chip {
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struct device *dev;
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struct clk *clk;
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unsigned long clk_rate;
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struct regmap *regmap;
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struct sti_pwm_compat_data *cdata;
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struct regmap_field *prescale;
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struct regmap_field *pwm_en;
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struct regmap_field *pwm_int_en;
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unsigned long *pwm_periods;
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struct pwm_chip chip;
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void __iomem *mmio;
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};
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static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = {
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[PWMCLK_PRESCALE] = REG_FIELD(STI_PWMCR, 0, 3),
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[PWM_EN] = REG_FIELD(STI_PWMCR, 9, 9),
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[PWM_INT_EN] = REG_FIELD(STI_INTEN, 0, 0),
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};
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static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip)
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{
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return container_of(chip, struct sti_pwm_chip, chip);
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}
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/*
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* Calculate the period values supported by the PWM for the
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* current clock rate.
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*/
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static void sti_pwm_calc_periods(struct sti_pwm_chip *pc)
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{
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struct sti_pwm_compat_data *cdata = pc->cdata;
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struct device *dev = pc->dev;
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unsigned long val;
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int i;
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/*
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* period_ns = (10^9 * (prescaler + 1) * (MAX_PWM_COUNT + 1)) / CLK_RATE
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*/
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val = NSEC_PER_SEC / pc->clk_rate;
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val *= cdata->max_pwm_cnt + 1;
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dev_dbg(dev, "possible periods for clkrate[HZ]:%lu\n", pc->clk_rate);
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for (i = 0; i <= cdata->max_prescale; i++) {
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pc->pwm_periods[i] = val * (i + 1);
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dev_dbg(dev, "prescale:%d, period[ns]:%lu\n",
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i, pc->pwm_periods[i]);
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}
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}
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static int sti_pwm_cmp_periods(const void *key, const void *elt)
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{
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unsigned long i = *(unsigned long *)key;
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unsigned long j = *(unsigned long *)elt;
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if (i < j)
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return -1;
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else
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return i == j ? 0 : 1;
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}
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/*
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* For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles.
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* The only way to change the period (apart from changing the PWM input clock)
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* is to change the PWM clock prescaler.
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* The prescaler is of 4 bits, so only 16 prescaler values and hence only
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* 16 possible period values are supported (for a particular clock rate).
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* The requested period will be applied only if it matches one of these
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* 16 values.
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*/
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static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
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struct sti_pwm_compat_data *cdata = pc->cdata;
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struct device *dev = pc->dev;
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unsigned int prescale, pwmvalx;
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unsigned long *found;
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int ret;
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/*
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* Search for matching period value. The corresponding index is our
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* prescale value
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*/
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found = bsearch(&period_ns, &pc->pwm_periods[0],
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cdata->max_prescale + 1, sizeof(unsigned long),
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sti_pwm_cmp_periods);
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if (!found) {
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dev_err(dev, "failed to find matching period\n");
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return -EINVAL;
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}
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prescale = found - &pc->pwm_periods[0];
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/*
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* When PWMVal == 0, PWM pulse = 1 local clock cycle.
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* When PWMVal == max_pwm_count,
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* PWM pulse = (max_pwm_count + 1) local cycles,
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* that is continuous pulse: signal never goes low.
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*/
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pwmvalx = cdata->max_pwm_cnt * duty_ns / period_ns;
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dev_dbg(dev, "prescale:%u, period:%i, duty:%i, pwmvalx:%u\n",
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prescale, period_ns, duty_ns, pwmvalx);
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/* Enable clock before writing to PWM registers */
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ret = clk_enable(pc->clk);
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if (ret)
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return ret;
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ret = regmap_field_write(pc->prescale, prescale);
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if (ret)
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goto clk_dis;
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ret = regmap_write(pc->regmap, STI_PWMVAL(pwm->hwpwm), pwmvalx);
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if (ret)
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goto clk_dis;
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ret = regmap_field_write(pc->pwm_int_en, 0);
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clk_dis:
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clk_disable(pc->clk);
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return ret;
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}
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static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
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struct device *dev = pc->dev;
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int ret;
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ret = clk_enable(pc->clk);
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if (ret)
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return ret;
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ret = regmap_field_write(pc->pwm_en, 1);
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if (ret)
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dev_err(dev, "%s,pwm_en write failed\n", __func__);
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return ret;
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}
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static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
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struct device *dev = pc->dev;
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unsigned int val;
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regmap_field_write(pc->pwm_en, 0);
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regmap_read(pc->regmap, STI_CNT, &val);
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dev_dbg(dev, "pwm counter :%u\n", val);
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clk_disable(pc->clk);
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}
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static const struct pwm_ops sti_pwm_ops = {
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.config = sti_pwm_config,
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.enable = sti_pwm_enable,
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.disable = sti_pwm_disable,
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.owner = THIS_MODULE,
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};
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static int sti_pwm_probe_dt(struct sti_pwm_chip *pc)
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{
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struct device *dev = pc->dev;
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const struct reg_field *reg_fields;
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struct device_node *np = dev->of_node;
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struct sti_pwm_compat_data *cdata = pc->cdata;
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u32 num_chan;
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of_property_read_u32(np, "st,pwm-num-chan", &num_chan);
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if (num_chan)
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cdata->num_chan = num_chan;
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reg_fields = cdata->reg_fields;
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pc->prescale = devm_regmap_field_alloc(dev, pc->regmap,
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reg_fields[PWMCLK_PRESCALE]);
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if (IS_ERR(pc->prescale))
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return PTR_ERR(pc->prescale);
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pc->pwm_en = devm_regmap_field_alloc(dev, pc->regmap,
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reg_fields[PWM_EN]);
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if (IS_ERR(pc->pwm_en))
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return PTR_ERR(pc->pwm_en);
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pc->pwm_int_en = devm_regmap_field_alloc(dev, pc->regmap,
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reg_fields[PWM_INT_EN]);
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if (IS_ERR(pc->pwm_int_en))
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return PTR_ERR(pc->pwm_int_en);
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return 0;
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}
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static const struct regmap_config sti_pwm_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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static int sti_pwm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct sti_pwm_compat_data *cdata;
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struct sti_pwm_chip *pc;
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struct resource *res;
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int ret;
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pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL);
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if (!cdata)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pc->mmio = devm_ioremap_resource(dev, res);
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if (IS_ERR(pc->mmio))
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return PTR_ERR(pc->mmio);
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pc->regmap = devm_regmap_init_mmio(dev, pc->mmio,
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&sti_pwm_regmap_config);
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if (IS_ERR(pc->regmap))
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return PTR_ERR(pc->regmap);
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/*
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* Setup PWM data with default values: some values could be replaced
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* with specific ones provided from Device Tree.
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*/
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cdata->reg_fields = &sti_pwm_regfields[0];
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cdata->max_prescale = 0xff;
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cdata->max_pwm_cnt = 255;
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cdata->num_chan = 1;
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pc->cdata = cdata;
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pc->dev = dev;
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ret = sti_pwm_probe_dt(pc);
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if (ret)
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return ret;
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pc->pwm_periods = devm_kzalloc(dev,
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sizeof(unsigned long) * (pc->cdata->max_prescale + 1),
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GFP_KERNEL);
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if (!pc->pwm_periods)
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return -ENOMEM;
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pc->clk = of_clk_get_by_name(dev->of_node, "pwm");
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if (IS_ERR(pc->clk)) {
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dev_err(dev, "failed to get PWM clock\n");
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return PTR_ERR(pc->clk);
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}
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pc->clk_rate = clk_get_rate(pc->clk);
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if (!pc->clk_rate) {
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dev_err(dev, "failed to get clock rate\n");
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return -EINVAL;
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}
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ret = clk_prepare(pc->clk);
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if (ret) {
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dev_err(dev, "failed to prepare clock\n");
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return ret;
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}
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sti_pwm_calc_periods(pc);
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pc->chip.dev = dev;
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pc->chip.ops = &sti_pwm_ops;
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pc->chip.base = -1;
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pc->chip.npwm = pc->cdata->num_chan;
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pc->chip.can_sleep = true;
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ret = pwmchip_add(&pc->chip);
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if (ret < 0) {
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clk_unprepare(pc->clk);
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return ret;
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}
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platform_set_drvdata(pdev, pc);
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return 0;
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}
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static int sti_pwm_remove(struct platform_device *pdev)
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{
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struct sti_pwm_chip *pc = platform_get_drvdata(pdev);
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unsigned int i;
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for (i = 0; i < pc->cdata->num_chan; i++)
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pwm_disable(&pc->chip.pwms[i]);
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clk_unprepare(pc->clk);
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return pwmchip_remove(&pc->chip);
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}
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static const struct of_device_id sti_pwm_of_match[] = {
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{ .compatible = "st,sti-pwm", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sti_pwm_of_match);
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static struct platform_driver sti_pwm_driver = {
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.driver = {
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.name = "sti-pwm",
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.of_match_table = sti_pwm_of_match,
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},
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.probe = sti_pwm_probe,
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.remove = sti_pwm_remove,
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};
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module_platform_driver(sti_pwm_driver);
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MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>");
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MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
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MODULE_LICENSE("GPL");
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