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drm/amd/powerplay: move set_clockgating_by_smu to pp func table
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
ae97988fc8
commit
3811f8f00c
5 changed files with 54 additions and 40 deletions
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@ -356,6 +356,10 @@ enum amdgpu_pcie_gen {
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((adev)->powerplay.pp_funcs->switch_power_profile(\
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(adev)->powerplay.pp_handle, type))
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#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
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((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
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(adev)->powerplay.pp_handle, msg_id))
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struct amdgpu_dpm {
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struct amdgpu_ps *ps;
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/* number of valid power states */
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@ -5984,7 +5984,6 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
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{
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uint32_t msg_id, pp_state = 0;
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uint32_t pp_support_state = 0;
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void *pp_handle = adev->powerplay.pp_handle;
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if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
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@ -6002,7 +6001,8 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
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PP_BLOCK_GFX_CG,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
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@ -6023,7 +6023,8 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
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PP_BLOCK_GFX_MG,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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return 0;
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@ -6035,7 +6036,6 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
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uint32_t msg_id, pp_state = 0;
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uint32_t pp_support_state = 0;
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void *pp_handle = adev->powerplay.pp_handle;
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if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
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@ -6053,7 +6053,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
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PP_BLOCK_GFX_CG,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
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@ -6072,7 +6073,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
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PP_BLOCK_GFX_3D,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
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@ -6093,7 +6095,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
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PP_BLOCK_GFX_MG,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
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@ -6108,7 +6111,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
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PP_BLOCK_GFX_RLC,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
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@ -6122,7 +6126,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
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PP_BLOCK_GFX_CP,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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return 0;
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@ -1254,7 +1254,6 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
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uint32_t msg_id, pp_state = 0;
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uint32_t pp_support_state = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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void *pp_handle = adev->powerplay.pp_handle;
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if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
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if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
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@ -1271,7 +1270,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
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PP_BLOCK_SYS_MC,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
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@ -1289,7 +1289,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
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PP_BLOCK_SYS_SDMA,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
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@ -1307,7 +1308,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
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PP_BLOCK_SYS_HDP,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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@ -1321,7 +1323,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
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PP_BLOCK_SYS_BIF,
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PP_STATE_SUPPORT_LS,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
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if (state == AMD_CG_STATE_UNGATE)
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@ -1333,7 +1336,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
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PP_BLOCK_SYS_BIF,
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PP_STATE_SUPPORT_CG,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
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@ -1347,7 +1351,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
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PP_BLOCK_SYS_DRM,
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PP_STATE_SUPPORT_LS,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
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@ -1361,7 +1366,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
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PP_BLOCK_SYS_ROM,
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PP_STATE_SUPPORT_CG,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
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amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
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}
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return 0;
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}
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@ -222,28 +222,6 @@ static int pp_sw_reset(void *handle)
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return 0;
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}
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int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id)
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{
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struct pp_hwmgr *hwmgr;
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struct pp_instance *pp_handle = (struct pp_instance *)handle;
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int ret = 0;
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ret = pp_check(pp_handle);
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if (!ret)
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return ret;
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hwmgr = pp_handle->hwmgr;
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if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
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pr_info("%s was not implemented.\n", __func__);
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return 0;
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}
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return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
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}
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static int pp_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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@ -335,6 +313,27 @@ static int pp_dpm_fw_loading_complete(void *handle)
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return 0;
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}
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static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
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{
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struct pp_hwmgr *hwmgr;
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struct pp_instance *pp_handle = (struct pp_instance *)handle;
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int ret = 0;
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ret = pp_check(pp_handle);
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if (ret)
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return ret;
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hwmgr = pp_handle->hwmgr;
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if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
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pr_info("%s was not implemented.\n", __func__);
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return 0;
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}
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return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
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}
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static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
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enum amd_dpm_forced_level *level)
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{
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@ -1177,6 +1176,7 @@ const struct amd_pm_funcs pp_dpm_funcs = {
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.get_power_profile_state = pp_dpm_get_power_profile_state,
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.set_power_profile_state = pp_dpm_set_power_profile_state,
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.switch_power_profile = pp_dpm_switch_power_profile,
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.set_clockgating_by_smu = pp_set_clockgating_by_smu,
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};
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int amd_powerplay_reset(void *handle)
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@ -304,6 +304,5 @@ int amd_powerplay_display_clock_voltage_request(void *handle,
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int amd_powerplay_get_display_mode_validation_clocks(void *handle,
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struct amd_pp_simple_clock_info *output);
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int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id);
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#endif /* _AMD_POWERPLAY_H_ */
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