Itanium fixes for 3.5 merge window
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPvQqdAAoJEKurIx+X31iBg6gP/0gclssJFuc509wn18ng+zmP QOfRqsQ/Qta0he4t5WuLzQ7Ht26RlivIVwd23tHcRdgQzdEztXB7J6iz/PwQ7l8A Cgf/BrZ1r7F54JQh06y9B6ClggB2VEwj711fqTQtr8nRazxfuj+3m5L+iVQjgzlq DGlcoFN1rfl2FZqzCPFChqZslyZMm5QVd9cHZaEfP2srU3Y52JbcbiErzxDdSK28 Q2jvX6iPalXEizk4oIXh8qz8KhnX29oTH+ujY1PtxaP6G+7cPJy+601GB5mAzG0K vn1tb1+Lwu1/gKJ3soO3elFX3PFW4TVlK/TF/ahnVXe8aDXkrftP1SsBsXQ+Xd6Y jFl2iNZkGKKuAIMu6+mjgQ9LWt3Xa0qTAIlDoOgRYK/OlWs3cGlCD07+rzsqtbcC amXS4eNa4AYwb5Qo5BFX2Hejqsock78nmG+AUOvmYOHHDNFEvmeNCfhDDcE+iHRq Nm0ZINAXXWqJTtMwrH/DaXO/U7LRbuwzMBd/hCX5aC5xcd2fwERDtisFyZfvDSX6 0vVflWYfUpUdnf/KeGHh4C3AFmroy3P9S0+aKJJQ4NZ7oQE/15zn7MRPWVC+6hzY /OgeoUQKaIh8Q/oEs8P+xOarl91sdF34ZgEkVHDM5Nuzt8EgUFxhMAvDJ+7h8npA fQ3y7YMjRDNIzpPIKGRQ =WOV+ -----END PGP SIGNATURE----- Merge tag 'ia64-3.5-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux Pull Itanium fixes from Tony Luck. * tag 'ia64-3.5-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux: [IA64] Liberate the signal layer from IA64 assembler [IA64] Add cmpxchg.h to exported userspace headers [IA64] Fix fast syscall version of getcpu() [IA64] Removed "task_size" element from thread_struct - it is now constant
This commit is contained in:
Linus Torvalds
commit
3813d4024a
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@ -1,6 +1,7 @@
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include include/asm-generic/Kbuild.asm
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header-y += break.h
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header-y += cmpxchg.h
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header-y += fpu.h
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header-y += gcc_intrin.h
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header-y += ia64regs.h
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@ -34,8 +34,7 @@
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* each (assuming 8KB page size), for a total of 8TB of user virtual
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* address space.
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*/
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#define TASK_SIZE_OF(tsk) ((tsk)->thread.task_size)
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#define TASK_SIZE TASK_SIZE_OF(current)
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#define TASK_SIZE DEFAULT_TASK_SIZE
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/*
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* This decides where the kernel will search for a free chunk of vm
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@ -280,7 +279,6 @@ struct thread_struct {
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__u8 pad[3];
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__u64 ksp; /* kernel stack pointer */
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__u64 map_base; /* base address for get_unmapped_area() */
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__u64 task_size; /* limit for task size */
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__u64 rbs_bot; /* the base address for the RBS */
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int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */
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@ -303,7 +301,6 @@ struct thread_struct {
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.ksp = 0, \
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.map_base = DEFAULT_MAP_BASE, \
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.rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \
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.task_size = DEFAULT_TASK_SIZE, \
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.last_fph_cpu = -1, \
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INIT_THREAD_PM \
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.dbr = {0, }, \
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@ -371,175 +371,6 @@ ENTRY(fsys_clock_gettime)
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br.many .gettime
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END(fsys_clock_gettime)
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/*
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* long fsys_rt_sigprocmask (int how, sigset_t *set, sigset_t *oset, size_t sigsetsize).
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*/
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#if _NSIG_WORDS != 1
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# error Sorry, fsys_rt_sigprocmask() needs to be updated for _NSIG_WORDS != 1.
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#endif
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ENTRY(fsys_rt_sigprocmask)
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.prologue
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.altrp b6
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.body
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add r2=IA64_TASK_BLOCKED_OFFSET,r16
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add r9=TI_FLAGS+IA64_TASK_SIZE,r16
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cmp4.ltu p6,p0=SIG_SETMASK,r32
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cmp.ne p15,p0=r0,r34 // oset != NULL?
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tnat.nz p8,p0=r34
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add r31=IA64_TASK_SIGHAND_OFFSET,r16
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;;
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ld8 r3=[r2] // read/prefetch current->blocked
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ld4 r9=[r9]
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tnat.nz.or p6,p0=r35
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cmp.ne.or p6,p0=_NSIG_WORDS*8,r35
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tnat.nz.or p6,p0=r32
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(p6) br.spnt.few .fail_einval // fail with EINVAL
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;;
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#ifdef CONFIG_SMP
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ld8 r31=[r31] // r31 <- current->sighand
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#endif
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and r9=TIF_ALLWORK_MASK,r9
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tnat.nz.or p8,p0=r33
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;;
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cmp.ne p7,p0=0,r9
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cmp.eq p6,p0=r0,r33 // set == NULL?
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add r31=IA64_SIGHAND_SIGLOCK_OFFSET,r31 // r31 <- current->sighand->siglock
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(p8) br.spnt.few .fail_efault // fail with EFAULT
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(p7) br.spnt.many fsys_fallback_syscall // got pending kernel work...
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(p6) br.dpnt.many .store_mask // -> short-circuit to just reading the signal mask
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/* Argh, we actually have to do some work and _update_ the signal mask: */
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EX(.fail_efault, probe.r.fault r33, 3) // verify user has read-access to *set
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EX(.fail_efault, ld8 r14=[r33]) // r14 <- *set
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mov r17=(1 << (SIGKILL - 1)) | (1 << (SIGSTOP - 1))
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;;
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RSM_PSR_I(p0, r18, r19) // mask interrupt delivery
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andcm r14=r14,r17 // filter out SIGKILL & SIGSTOP
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mov r8=EINVAL // default to EINVAL
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#ifdef CONFIG_SMP
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// __ticket_spin_trylock(r31)
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ld4 r17=[r31]
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;;
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mov.m ar.ccv=r17
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extr.u r9=r17,17,15
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adds r19=1,r17
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extr.u r18=r17,0,15
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;;
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cmp.eq p6,p7=r9,r18
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;;
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(p6) cmpxchg4.acq r9=[r31],r19,ar.ccv
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(p6) dep.z r20=r19,1,15 // next serving ticket for unlock
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(p7) br.cond.spnt.many .lock_contention
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;;
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cmp4.eq p0,p7=r9,r17
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adds r31=2,r31
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(p7) br.cond.spnt.many .lock_contention
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ld8 r3=[r2] // re-read current->blocked now that we hold the lock
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;;
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#else
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ld8 r3=[r2] // re-read current->blocked now that we hold the lock
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#endif
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add r18=IA64_TASK_PENDING_OFFSET+IA64_SIGPENDING_SIGNAL_OFFSET,r16
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add r19=IA64_TASK_SIGNAL_OFFSET,r16
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cmp4.eq p6,p0=SIG_BLOCK,r32
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;;
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ld8 r19=[r19] // r19 <- current->signal
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cmp4.eq p7,p0=SIG_UNBLOCK,r32
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cmp4.eq p8,p0=SIG_SETMASK,r32
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;;
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ld8 r18=[r18] // r18 <- current->pending.signal
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.pred.rel.mutex p6,p7,p8
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(p6) or r14=r3,r14 // SIG_BLOCK
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(p7) andcm r14=r3,r14 // SIG_UNBLOCK
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(p8) mov r14=r14 // SIG_SETMASK
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(p6) mov r8=0 // clear error code
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// recalc_sigpending()
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add r17=IA64_SIGNAL_GROUP_STOP_COUNT_OFFSET,r19
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add r19=IA64_SIGNAL_SHARED_PENDING_OFFSET+IA64_SIGPENDING_SIGNAL_OFFSET,r19
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;;
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ld4 r17=[r17] // r17 <- current->signal->group_stop_count
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(p7) mov r8=0 // clear error code
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ld8 r19=[r19] // r19 <- current->signal->shared_pending
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;;
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cmp4.gt p6,p7=r17,r0 // p6/p7 <- (current->signal->group_stop_count > 0)?
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(p8) mov r8=0 // clear error code
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or r18=r18,r19 // r18 <- current->pending | current->signal->shared_pending
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;;
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// r18 <- (current->pending | current->signal->shared_pending) & ~current->blocked:
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andcm r18=r18,r14
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add r9=TI_FLAGS+IA64_TASK_SIZE,r16
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;;
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(p7) cmp.ne.or.andcm p6,p7=r18,r0 // p6/p7 <- signal pending
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mov r19=0 // i must not leak kernel bits...
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(p6) br.cond.dpnt.many .sig_pending
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;;
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1: ld4 r17=[r9] // r17 <- current->thread_info->flags
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;;
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mov ar.ccv=r17
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and r18=~_TIF_SIGPENDING,r17 // r18 <- r17 & ~(1 << TIF_SIGPENDING)
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;;
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st8 [r2]=r14 // update current->blocked with new mask
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cmpxchg4.acq r8=[r9],r18,ar.ccv // current->thread_info->flags <- r18
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;;
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cmp.ne p6,p0=r17,r8 // update failed?
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(p6) br.cond.spnt.few 1b // yes -> retry
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#ifdef CONFIG_SMP
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// __ticket_spin_unlock(r31)
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st2.rel [r31]=r20
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mov r20=0 // i must not leak kernel bits...
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#endif
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SSM_PSR_I(p0, p9, r31)
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;;
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srlz.d // ensure psr.i is set again
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mov r18=0 // i must not leak kernel bits...
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.store_mask:
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EX(.fail_efault, (p15) probe.w.fault r34, 3) // verify user has write-access to *oset
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EX(.fail_efault, (p15) st8 [r34]=r3)
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mov r2=0 // i must not leak kernel bits...
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mov r3=0 // i must not leak kernel bits...
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mov r8=0 // return 0
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mov r9=0 // i must not leak kernel bits...
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mov r14=0 // i must not leak kernel bits...
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mov r17=0 // i must not leak kernel bits...
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mov r31=0 // i must not leak kernel bits...
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FSYS_RETURN
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.sig_pending:
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#ifdef CONFIG_SMP
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// __ticket_spin_unlock(r31)
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st2.rel [r31]=r20 // release the lock
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#endif
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SSM_PSR_I(p0, p9, r17)
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;;
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srlz.d
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br.sptk.many fsys_fallback_syscall // with signal pending, do the heavy-weight syscall
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#ifdef CONFIG_SMP
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.lock_contention:
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/* Rather than spinning here, fall back on doing a heavy-weight syscall. */
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SSM_PSR_I(p0, p9, r17)
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;;
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srlz.d
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br.sptk.many fsys_fallback_syscall
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#endif
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END(fsys_rt_sigprocmask)
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/*
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* fsys_getcpu doesn't use the third parameter in this implementation. It reads
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* current_thread_info()->cpu and corresponding node in cpu_to_node_map.
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@ -559,11 +390,15 @@ ENTRY(fsys_getcpu)
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;;
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tnat.nz p7,p0 = r33 // I guard against NaT argument
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(p7) br.cond.spnt.few .fail_einval // B
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;;
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cmp.ne p6,p0=r32,r0
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cmp.ne p7,p0=r33,r0
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;;
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#ifdef CONFIG_NUMA
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movl r17=cpu_to_node_map
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;;
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EX(.fail_efault, probe.w.fault r32, 3) // M This takes 5 cycles
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EX(.fail_efault, probe.w.fault r33, 3) // M This takes 5 cycles
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EX(.fail_efault, (p6) probe.w.fault r32, 3) // M This takes 5 cycles
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EX(.fail_efault, (p7) probe.w.fault r33, 3) // M This takes 5 cycles
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shladd r18=r3,1,r17
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;;
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ld2 r20=[r18] // r20 = cpu_to_node_map[cpu]
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@ -573,20 +408,20 @@ EX(.fail_efault, probe.w.fault r33, 3) // M This takes 5 cycles
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(p8) br.spnt.many fsys_fallback_syscall
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;;
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;;
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EX(.fail_efault, st4 [r32] = r3)
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EX(.fail_efault, st2 [r33] = r20)
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EX(.fail_efault, (p6) st4 [r32] = r3)
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EX(.fail_efault, (p7) st2 [r33] = r20)
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mov r8=0
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;;
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#else
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EX(.fail_efault, probe.w.fault r32, 3) // M This takes 5 cycles
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EX(.fail_efault, probe.w.fault r33, 3) // M This takes 5 cycles
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EX(.fail_efault, (p6) probe.w.fault r32, 3) // M This takes 5 cycles
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EX(.fail_efault, (p7) probe.w.fault r33, 3) // M This takes 5 cycles
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and r2 = TIF_ALLWORK_MASK,r2
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;;
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cmp.ne p8,p0=0,r2
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(p8) br.spnt.many fsys_fallback_syscall
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;;
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EX(.fail_efault, st4 [r32] = r3)
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EX(.fail_efault, st2 [r33] = r0)
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EX(.fail_efault, (p6) st4 [r32] = r3)
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EX(.fail_efault, (p7) st2 [r33] = r0)
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mov r8=0
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;;
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#endif
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@ -916,7 +751,7 @@ paravirt_fsyscall_table:
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data8 0 // sigaltstack
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data8 0 // rt_sigaction
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data8 0 // rt_sigpending
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data8 fsys_rt_sigprocmask // rt_sigprocmask
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data8 0 // rt_sigprocmask
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data8 0 // rt_sigqueueinfo // 1180
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data8 0 // rt_sigreturn
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data8 0 // rt_sigsuspend
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