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rtw89: coex: Update Wi-Fi driver/firmware TDMA cycle report for RTL8852c

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Because RTL8852c firmware handshake use different structure definition
with RTL8852a, so it's necessary to update a version for RTL8852c.

Signed-off-by: Ching-Te Ku <ku920601@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220725023509.43114-10-pkshih@realtek.com
This commit is contained in:
Ching-Te Ku 2022-07-25 10:35:09 +08:00 committed by Kalle Valo
parent 747dc30e64
commit 3832a54249
2 changed files with 113 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

61
drivers/net/wireless/realtek/rtw89/coex.c
View file

@ -912,12 +912,14 @@ static u32 _chk_btc_report(struct rtw89_dev *rtwdev,
struct rtw89_btc_fbtc_rpt_ctrl *prpt;
struct rtw89_btc_fbtc_rpt_ctrl_v1 *prpt_v1;
struct rtw89_btc_fbtc_cysta *pcysta_le32 = NULL;
struct rtw89_btc_fbtc_cysta_v1 *pcysta_v1 = NULL;
struct rtw89_btc_fbtc_cysta_cpu pcysta[1];
struct rtw89_btc_prpt *btc_prpt = NULL;
struct rtw89_btc_fbtc_slot *rtp_slot = NULL;
u8 rpt_type = 0, *rpt_content = NULL, *pfinfo = NULL;
u16 wl_slot_set = 0;
u16 wl_slot_set = 0, wl_slot_real = 0;
u32 trace_step = btc->ctrl.trace_step, rpt_len = 0, diff_t;
u32 cnt_leak_slot = 0, bt_slot_real = 0, cnt_rx_imr = 0;
u8 i;
rtw89_debug(rtwdev, RTW89_DBG_BTC,
@ -975,10 +977,16 @@ static u32 _chk_btc_report(struct rtw89_dev *rtwdev,
break;
case BTC_RPT_TYPE_CYSTA:
pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_cysta.finfo);
pcysta_le32 = &pfwinfo->rpt_fbtc_cysta.finfo;
rtw89_btc_fbtc_cysta_to_cpu(pcysta_le32, pcysta);
pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_cysta.finfo);
if (chip->chip_id == RTL8852A) {
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_cysta.finfo);
pcysta_le32 = &pfwinfo->rpt_fbtc_cysta.finfo;
rtw89_btc_fbtc_cysta_to_cpu(pcysta_le32, pcysta);
pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_cysta.finfo);
} else {
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_cysta.finfo_v1);
pcysta_v1 = &pfwinfo->rpt_fbtc_cysta.finfo_v1;
pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_cysta.finfo_v1);
}
pcinfo->req_fver = chip->fcxcysta_ver;
pcinfo->rx_len = rpt_len;
pcinfo->rx_cnt++;
@ -1177,7 +1185,7 @@ static u32 _chk_btc_report(struct rtw89_dev *rtwdev,
sizeof(dm->slot_now)));
}
if (rpt_type == BTC_RPT_TYPE_CYSTA &&
if (rpt_type == BTC_RPT_TYPE_CYSTA && chip->chip_id == RTL8852A &&
pcysta->cycles >= BTC_CYSTA_CHK_PERIOD) {
/* Check Leak-AP */
if (pcysta->slot_cnt[CXST_LK] != 0 &&
@ -1200,8 +1208,47 @@ static u32 _chk_btc_report(struct rtw89_dev *rtwdev,
}
_chk_btc_err(rtwdev, BTC_DCNT_W1_FREEZE, pcysta->slot_cnt[CXST_W1]);
_chk_btc_err(rtwdev, BTC_DCNT_W1_FREEZE, pcysta->slot_cnt[CXST_W1]);
_chk_btc_err(rtwdev, BTC_DCNT_W1_FREEZE, pcysta->slot_cnt[CXST_B1]);
_chk_btc_err(rtwdev, BTC_DCNT_CYCLE_FREEZE, (u32)pcysta->cycles);
} else if (rpt_type == BTC_RPT_TYPE_CYSTA && pcysta_v1 &&
le16_to_cpu(pcysta_v1->cycles) >= BTC_CYSTA_CHK_PERIOD) {
cnt_leak_slot = le32_to_cpu(pcysta_v1->slot_cnt[CXST_LK]);
cnt_rx_imr = le32_to_cpu(pcysta_v1->leak_slot.cnt_rximr);
/* Check Leak-AP */
if (cnt_leak_slot != 0 && cnt_rx_imr != 0 &&
dm->tdma_now.rxflctrl) {
if (cnt_leak_slot < BTC_LEAK_AP_TH * cnt_rx_imr)
dm->leak_ap = 1;
}
/* Check diff time between real WL slot and W1 slot */
if (dm->tdma_now.type == CXTDMA_OFF) {
wl_slot_set = le16_to_cpu(dm->slot_now[CXST_W1].dur);
wl_slot_real = le16_to_cpu(pcysta_v1->cycle_time.tavg[CXT_WL]);
if (wl_slot_real > wl_slot_set) {
diff_t = wl_slot_real - wl_slot_set;
_chk_btc_err(rtwdev, BTC_DCNT_WL_SLOT_DRIFT, diff_t);
}
}
/* Check diff time between real BT slot and EBT/E5G slot */
if (dm->tdma_now.type == CXTDMA_OFF &&
dm->tdma_now.ext_ctrl == CXECTL_EXT &&
btc->bt_req_len != 0) {
bt_slot_real = le16_to_cpu(pcysta_v1->cycle_time.tavg[CXT_BT]);
if (btc->bt_req_len > bt_slot_real) {
diff_t = btc->bt_req_len - bt_slot_real;
_chk_btc_err(rtwdev, BTC_DCNT_BT_SLOT_DRIFT, diff_t);
}
}
_chk_btc_err(rtwdev, BTC_DCNT_W1_FREEZE,
le32_to_cpu(pcysta_v1->slot_cnt[CXST_W1]));
_chk_btc_err(rtwdev, BTC_DCNT_B1_FREEZE,
le32_to_cpu(pcysta_v1->slot_cnt[CXST_B1]));
_chk_btc_err(rtwdev, BTC_DCNT_CYCLE_FREEZE,
(u32)le16_to_cpu(pcysta_v1->cycles));
}
if (rpt_type == BTC_RPT_TYPE_CTRL && chip->chip_id == RTL8852A) {

60
drivers/net/wireless/realtek/rtw89/core.h
View file

@ -863,6 +863,7 @@ enum rtw89_btc_dcnt {
BTC_DCNT_SLOT_NONSYNC,
BTC_DCNT_BTCNT_FREEZE,
BTC_DCNT_WL_SLOT_DRIFT,
BTC_DCNT_BT_SLOT_DRIFT,
BTC_DCNT_WL_STA_LAST,
BTC_DCNT_NUM,
};
@ -1653,6 +1654,60 @@ struct rtw89_btc_fbtc_cysta { /* statistics for cycles */
__le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
} __packed;
struct rtw89_btc_fbtc_fdd_try_info {
__le16 cycles[CXT_FLCTRL_MAX];
__le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
__le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
} __packed;
struct rtw89_btc_fbtc_cycle_time_info {
__le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
__le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
__le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
} __packed;
struct rtw89_btc_fbtc_a2dp_trx_stat {
u8 empty_cnt;
u8 retry_cnt;
u8 tx_rate;
u8 tx_cnt;
u8 ack_cnt;
u8 nack_cnt;
u8 rsvd1;
u8 rsvd2;
} __packed;
struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
__le16 cnt; /* a2dp empty cnt */
__le16 cnt_timeout; /* a2dp empty timeout cnt*/
__le16 tavg; /* avg a2dp empty time */
__le16 tmax; /* max a2dp empty time */
} __packed;
struct rtw89_btc_fbtc_cycle_leak_info {
__le32 cnt_rximr; /* the rximr occur at leak slot */
__le16 tavg; /* avg leak-slot time */
__le16 tmax; /* max leak-slot time */
} __packed;
struct rtw89_btc_fbtc_cysta_v1 { /* statistics for cycles */
u8 fver;
u8 rsvd;
__le16 cycles; /* total cycle number */
__le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
struct rtw89_btc_fbtc_cycle_time_info cycle_time;
struct rtw89_btc_fbtc_fdd_try_info fdd_try;
struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
__le32 slot_cnt[CXST_MAX]; /* slot count */
__le32 bcn_cnt[CXBCN_MAX];
__le32 collision_cnt; /* counter for event/timer occur at the same time */
__le32 skip_cnt;
__le32 except_cnt;
__le32 except_map;
} __packed;
struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */
u8 fver; /* chip_info::fcxnullsta_ver */
u8 rsvd;
@ -1829,7 +1884,10 @@ struct rtw89_btc_rpt_fbtc_slots {
struct rtw89_btc_rpt_fbtc_cysta {
struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
struct rtw89_btc_fbtc_cysta finfo; /* info from fw */
union {
struct rtw89_btc_fbtc_cysta finfo; /* info from fw for 52A*/
struct rtw89_btc_fbtc_cysta_v1 finfo_v1; /* info from fw for 52C*/
};
};
struct rtw89_btc_rpt_fbtc_step {