mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-02 07:04:24 +00:00
powerpc: drop MPC8540_ADS and MPC8560_ADS platform support
Based on the revision history in the manual(s), these e500-v1 platforms were first available around 2002. Like a lot of evaluation boards, they attempted to provide break-out connectors for all possible features, and that combined with four PCI-X slots (and the age/era) meant for a considerably large board. As I recall it, from a Linux point of view, the biggest difference between 8540 and 8560 was in the UART implementation, and that is reflected in a diff of the defconfigs. In any case, these are over 20 years old, and by today's standards only have a small amount of DDR1 memory, and were not widely available. Given that, it makes sense to remove support from them in 2023. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230620043300.197546-2-paul.gortmaker@windriver.com
This commit is contained in:
Paul Gortmaker
Michael Ellerman
parent
e66effaf61
commit
384e338a91
8 changed files with 0 additions and 1008 deletions
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@ -342,8 +342,6 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.mpc8349emitx \
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image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
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# Board ports in arch/powerpc/platform/85xx/Kconfig
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image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
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image-$(CONFIG_MPC8560_ADS) += cuImage.mpc8560ads
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image-$(CONFIG_MPC85xx_CDS) += cuImage.mpc8541cds \
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cuImage.mpc8548cds_32b \
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cuImage.mpc8555cds
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@ -1,355 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MPC8540 ADS Device Tree Source
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*
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* Copyright 2006, 2008 Freescale Semiconductor Inc.
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*/
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/dts-v1/;
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/include/ "e500v1_power_isa.dtsi"
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/ {
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model = "MPC8540ADS";
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compatible = "MPC8540ADS", "MPC85xxADS";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8540@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>; // 33 MHz, from uboot
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bus-frequency = <0>; // 166 MHz
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clock-frequency = <0>; // 825 MHz, from uboot
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x8000000>; // 128M at 0x0
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};
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soc8540@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x100000>;
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bus-frequency = <0>;
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <8>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8540-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,mpc8540-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8540-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8540-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8540-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8540-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8540-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0x1>;
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <7 1>;
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reg = <0x3>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 2 36 2 40 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet2: ethernet@26000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <2>;
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device_type = "network";
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model = "FEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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ranges = <0x0 0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <41 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi2>;
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phy-handle = <&phy3>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4500 0x100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4600 0x100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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};
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pci0: pci@e0008000 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x02 */
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0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
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0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
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0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
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0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
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/* IDSEL 0x03 */
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0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
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0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
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0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
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0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x04 */
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0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
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0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
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0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
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0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
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/* IDSEL 0x05 */
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0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
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0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
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0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
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0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
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/* IDSEL 0x0c */
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0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
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0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
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0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
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0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
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/* IDSEL 0x0d */
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0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
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0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
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0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
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0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x0e */
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0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
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0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
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0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
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0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
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/* IDSEL 0x0f */
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0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
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0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
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0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
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0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
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/* IDSEL 0x12 */
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0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
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0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
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0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
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0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
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/* IDSEL 0x13 */
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0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
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0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
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0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
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0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x14 */
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0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
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0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
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0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
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0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
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/* IDSEL 0x15 */
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0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
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0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
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0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
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0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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bus-range = <0 0>;
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ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008000 0x1000>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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};
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};
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@ -1,388 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MPC8560 ADS Device Tree Source
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*
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* Copyright 2006, 2008 Freescale Semiconductor Inc.
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*/
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/dts-v1/;
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/include/ "e500v1_power_isa.dtsi"
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/ {
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model = "MPC8560ADS";
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compatible = "MPC8560ADS", "MPC85xxADS";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8560@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <82500000>;
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bus-frequency = <330000000>;
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clock-frequency = <825000000>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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soc8560@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x100000>;
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bus-frequency = <330000000>;
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <8>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8560-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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||||
compatible = "fsl,mpc8540-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2, 256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <7 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <7 1>;
|
||||
reg = <0x3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
cpm@919c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
|
||||
reg = <0x919c0 0x30>;
|
||||
ranges;
|
||||
|
||||
muram@80000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x80000 0x10000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0x0 0x4000 0x9000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@919f0 {
|
||||
compatible = "fsl,mpc8560-brg",
|
||||
"fsl,cpm2-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x919f0 0x10 0x915f0 0x10>;
|
||||
clock-frequency = <165000000>;
|
||||
};
|
||||
|
||||
cpmpic: pic@90c00 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <46 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x90c00 0x80>;
|
||||
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
|
||||
};
|
||||
|
||||
serial0: serial@91a00 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8560-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
reg = <0x91a00 0x20 0x88000 0x100>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x800000>;
|
||||
current-speed = <115200>;
|
||||
interrupts = <40 8>;
|
||||
interrupt-parent = <&cpmpic>;
|
||||
};
|
||||
|
||||
serial1: serial@91a20 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8560-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
reg = <0x91a20 0x20 0x88100 0x100>;
|
||||
fsl,cpm-brg = <2>;
|
||||
fsl,cpm-command = <0x4a00000>;
|
||||
current-speed = <115200>;
|
||||
interrupts = <41 8>;
|
||||
interrupt-parent = <&cpmpic>;
|
||||
};
|
||||
|
||||
enet2: ethernet@91320 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8560-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
fsl,cpm-command = <0x16200300>;
|
||||
interrupts = <33 8>;
|
||||
interrupt-parent = <&cpmpic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet3: ethernet@91340 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8560-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
fsl,cpm-command = <0x1a400300>;
|
||||
interrupts = <34 8>;
|
||||
interrupt-parent = <&cpmpic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008000 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xe0008000 0x1000>;
|
||||
clock-frequency = <66666666>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x2 */
|
||||
0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
|
||||
0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
|
||||
0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
|
||||
0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
|
||||
|
||||
/* IDSEL 0x3 */
|
||||
0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
|
||||
/* IDSEL 0x4 */
|
||||
0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
|
||||
0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
|
||||
0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
|
||||
0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
|
||||
|
||||
/* IDSEL 0x5 */
|
||||
0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||
0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||
0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||
0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
|
||||
|
||||
/* IDSEL 12 */
|
||||
0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
|
||||
0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
|
||||
0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
|
||||
0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
|
||||
|
||||
/* IDSEL 13 */
|
||||
0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
|
||||
/* IDSEL 14*/
|
||||
0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
|
||||
0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
|
||||
0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
|
||||
0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
|
||||
|
||||
/* IDSEL 15 */
|
||||
0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||
0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||
0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||
0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
|
||||
|
||||
/* IDSEL 18 */
|
||||
0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
|
||||
0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
|
||||
0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
|
||||
0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
|
||||
|
||||
/* IDSEL 19 */
|
||||
0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
|
||||
/* IDSEL 20 */
|
||||
0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
|
||||
0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
|
||||
0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
|
||||
0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
|
||||
|
||||
/* IDSEL 21 */
|
||||
0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||
0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||
0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||
0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
CONFIG_PPC_85xx=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_MSDOS_PARTITION is not set
|
||||
CONFIG_MPC8540_ADS=y
|
||||
CONFIG_GEN_RTC=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_MATH_EMULATION=y
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=32768
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_GIANFAR=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
CONFIG_PPC_85xx=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_MSDOS_PARTITION is not set
|
||||
CONFIG_MPC8560_ADS=y
|
||||
CONFIG_GEN_RTC=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_MATH_EMULATION=y
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_DEBUG=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=32768
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_FS_ENET=y
|
||||
# CONFIG_FS_ENET_HAS_SCC is not set
|
||||
CONFIG_GIANFAR=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_DAVICOM_PHY=y
|
||||
CONFIG_MARVELL_PHY=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_CPM=y
|
||||
CONFIG_SERIAL_CPM_CONSOLE=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
|
|
@ -1,7 +1,5 @@
|
|||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_MPC8536_DS=y
|
||||
CONFIG_MPC8540_ADS=y
|
||||
CONFIG_MPC8560_ADS=y
|
||||
CONFIG_MPC85xx_CDS=y
|
||||
CONFIG_MPC85xx_DS=y
|
||||
CONFIG_MPC85xx_MDS=y
|
||||
|
|
|
|||
|
|
@ -12,8 +12,6 @@ obj-y += common.o
|
|||
obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
|
||||
obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o
|
||||
obj-$(CONFIG_C293_PCIE) += c293pcie.o
|
||||
obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
|
||||
obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
|
||||
obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
|
||||
obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
|
||||
obj8259-$(CONFIG_PPC_I8259) += mpc85xx_8259.o
|
||||
|
|
|
|||
|
|
@ -1,162 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* MPC85xx setup and early boot code plus other random bits.
|
||||
*
|
||||
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Copyright 2005 Freescale Semiconductor Inc.
|
||||
*/
|
||||
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/mpic.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/udbg.h>
|
||||
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
|
||||
#ifdef CONFIG_CPM2
|
||||
#include <asm/cpm2.h>
|
||||
#include <sysdev/cpm2_pic.h>
|
||||
#endif
|
||||
|
||||
#include "mpc85xx.h"
|
||||
|
||||
static void __init mpc85xx_ads_pic_init(void)
|
||||
{
|
||||
struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
|
||||
0, 256, " OpenPIC ");
|
||||
BUG_ON(mpic == NULL);
|
||||
mpic_init(mpic);
|
||||
|
||||
mpc85xx_cpm2_pic_init();
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup the architecture
|
||||
*/
|
||||
#ifdef CONFIG_CPM2
|
||||
struct cpm_pin {
|
||||
int port, pin, flags;
|
||||
};
|
||||
|
||||
static const struct cpm_pin mpc8560_ads_pins[] = {
|
||||
/* SCC1 */
|
||||
{3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
|
||||
{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
|
||||
/* SCC2 */
|
||||
{2, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{2, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
|
||||
/* FCC2 */
|
||||
{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
|
||||
{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
|
||||
{2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
|
||||
|
||||
/* FCC3 */
|
||||
{1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK16 */
|
||||
{2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK15 */
|
||||
{2, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
};
|
||||
|
||||
static void __init init_ioports(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
|
||||
const struct cpm_pin *pin = &mpc8560_ads_pins[i];
|
||||
cpm2_set_pin(pin->port, pin->pin, pin->flags);
|
||||
}
|
||||
|
||||
cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
|
||||
cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
|
||||
cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
|
||||
cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
|
||||
cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
|
||||
cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
|
||||
cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
|
||||
cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init mpc85xx_ads_setup_arch(void)
|
||||
{
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
|
||||
|
||||
#ifdef CONFIG_CPM2
|
||||
cpm2_reset();
|
||||
init_ioports();
|
||||
#endif
|
||||
|
||||
fsl_pci_assign_primary();
|
||||
}
|
||||
|
||||
static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
|
||||
{
|
||||
uint pvid, svid, phid1;
|
||||
|
||||
pvid = mfspr(SPRN_PVR);
|
||||
svid = mfspr(SPRN_SVR);
|
||||
|
||||
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
|
||||
seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
|
||||
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
|
||||
|
||||
/* Display cpu Pll setting */
|
||||
phid1 = mfspr(SPRN_HID1);
|
||||
seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
|
||||
}
|
||||
|
||||
machine_arch_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
|
||||
|
||||
define_machine(mpc85xx_ads) {
|
||||
.name = "MPC85xx ADS",
|
||||
.compatible = "MPC85xxADS",
|
||||
.setup_arch = mpc85xx_ads_setup_arch,
|
||||
.init_IRQ = mpc85xx_ads_pic_init,
|
||||
.show_cpuinfo = mpc85xx_ads_show_cpuinfo,
|
||||
.get_irq = mpic_get_irq,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
Loading…
Reference in a new issue