dt-bindings: usb: Convert DWC USB3 bindings to DT schema
DWC USB3 DT node is supposed to be compliant with the Generic xHCI Controller schema, but with additional vendor-specific properties, the controller-specific reference clocks and PHYs. So let's convert the currently available legacy text-based DWC USB3 bindings to the DT schema and make sure the DWC USB3 nodes are also validated against the usb-xhci.yaml schema. Note 1. we have to discard the nodename restriction of being prefixed with "dwc3@" string, since in accordance with the usb-hcd.yaml schema USB nodes are supposed to be named as "^usb(@.*)". Note 2. The clock-related properties are marked as optional to match the DWC USB3 driver expectation and to improve the bindings mainainability so in case if there is a glue-node it would the responsible for the clocks initialization. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20201210090944.16283-11-Sergey.Semin@baikalelectronics.ru Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Serge Semin
Greg Kroah-Hartman
parent
55e945593b
commit
389d776588
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@ -1,128 +0,0 @@
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synopsys DWC3 CORE
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DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
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as described in 'usb/generic.txt'
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Required properties:
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- compatible: must be "snps,dwc3"
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- reg : Address and length of the register set for the device
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- interrupts: Interrupts used by the dwc3 controller.
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- clock-names: list of clock names. Ideally should be "ref",
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"bus_early", "suspend" but may be less or more.
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- clocks: list of phandle and clock specifier pairs corresponding to
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entries in the clock-names property.
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Exception for clocks:
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clocks are optional if the parent node (i.e. glue-layer) is compatible to
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one of the following:
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"cavium,octeon-7130-usb-uctl"
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"qcom,dwc3"
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"samsung,exynos5250-dwusb3"
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"samsung,exynos5433-dwusb3"
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"samsung,exynos7-dwusb3"
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"sprd,sc9860-dwc3"
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"st,stih407-dwc3"
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"ti,am437x-dwc3"
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"ti,dwc3"
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"ti,keystone-dwc3"
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"rockchip,rk3399-dwc3"
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"xlnx,zynqmp-dwc3"
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Optional properties:
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- usb-phy : array of phandle for the PHY device. The first element
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in the array is expected to be a handle to the USB2/HS PHY and
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the second element is expected to be a handle to the USB3/SS PHY
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- phys: from the *Generic PHY* bindings
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- phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy"
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or "usb3-phy".
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- resets: set of phandle and reset specifier pairs
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- snps,usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
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- snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
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- snps,dis-start-transfer-quirk: when set, disable isoc START TRANSFER command
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failure SW work-around for DWC_usb31 version 1.70a-ea06
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and prior.
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- snps,disable_scramble_quirk: true when SW should disable data scrambling.
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Only really useful for FPGA builds.
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- snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
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- snps,lpm-nyet-threshold: LPM NYET threshold
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- snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk
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- snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
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- snps,req_p1p2p3_quirk: when set, the core will always request for
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P1/P2/P3 transition sequence.
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- snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain
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amount of 8B10B errors occur.
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- snps,del_phy_power_chg_quirk: when set core will delay PHY power change
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from P0 to P1/P2/P3.
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- snps,lfps_filter_quirk: when set core will filter LFPS reception.
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- snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start
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Polling LFPS after RX.Detect.
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- snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value.
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- snps,tx_de_emphasis: the value driven to the PHY is controlled by the
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LTSSM during USB3 Compliance mode.
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- snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy.
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- snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy.
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- snps,dis_enblslpm_quirk: when set clears the enblslpm in GUSB2PHYCFG,
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disabling the suspend signal to the PHY.
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- snps,dis-u1-entry-quirk: set if link entering into U1 needs to be disabled.
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- snps,dis-u2-entry-quirk: set if link entering into U2 needs to be disabled.
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- snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection
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in PHY P3 power state.
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- snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists
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in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
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a free-running PHY clock.
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- snps,dis-del-phy-power-chg-quirk: when set core will change PHY power
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from P0 to P1/P2/P3 without delay.
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- snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check
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during HS transmit.
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- snps,parkmode-disable-ss-quirk: when set, all SuperSpeed bus instances in
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park mode are disabled.
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- snps,dis_metastability_quirk: when set, disable metastability workaround.
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CAUTION: use only if you are absolutely sure of it.
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- snps,dis-split-quirk: when set, change the way URBs are handled by the
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driver. Needed to avoid -EPROTO errors with usbhid
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on some devices (Hikey 970).
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- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
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utmi_l1_suspend_n, false when asserts utmi_sleep_n
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- snps,hird-threshold: HIRD threshold
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- snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for
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UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3.
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- snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
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register for post-silicon frame length adjustment when the
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fladj_30mhz_sdbnd signal is invalid or incorrect.
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- snps,rx-thr-num-pkt-prd: periodic ESS RX packet threshold count - host mode
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only. Set this and rx-max-burst-prd to a valid,
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non-zero value 1-16 (DWC_usb31 programming guide
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section 1.2.4) to enable periodic ESS RX threshold.
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- snps,rx-max-burst-prd: max periodic ESS RX burst size - host mode only. Set
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this and rx-thr-num-pkt-prd to a valid, non-zero value
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1-16 (DWC_usb31 programming guide section 1.2.4) to
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enable periodic ESS RX threshold.
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- snps,tx-thr-num-pkt-prd: periodic ESS TX packet threshold count - host mode
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only. Set this and tx-max-burst-prd to a valid,
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non-zero value 1-16 (DWC_usb31 programming guide
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section 1.2.3) to enable periodic ESS TX threshold.
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- snps,tx-max-burst-prd: max periodic ESS TX burst size - host mode only. Set
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this and tx-thr-num-pkt-prd to a valid, non-zero value
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1-16 (DWC_usb31 programming guide section 1.2.3) to
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enable periodic ESS TX threshold.
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- <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
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- snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
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register, undefined length INCR burst type enable and INCRx type.
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When just one value, which means INCRX burst mode enabled. When
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more than one value, which means undefined length INCR burst type
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enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256.
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- in addition all properties from usb-xhci.txt from the current directory are
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supported as well
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This is usually a subnode to DWC3 glue to which it is connected.
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dwc3@4a030000 {
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compatible = "snps,dwc3";
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reg = <0x4a030000 0xcfff>;
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interrupts = <0 92 4>
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usb-phy = <&usb2_phy>, <&usb3,phy>;
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snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
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};
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@ -0,0 +1,312 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare USB3 Controller
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maintainers:
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- Felipe Balbi <balbi@kernel.org>
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description:
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This is usually a subnode to DWC3 glue to which it is connected, but can also
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be presented as a standalone DT node with an optional vendor-specific
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compatible string.
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allOf:
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- $ref: usb-drd.yaml#
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- if:
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properties:
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dr_mode:
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const: peripheral
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required:
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- dr_mode
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then:
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$ref: usb.yaml#
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else:
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$ref: usb-xhci.yaml#
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properties:
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compatible:
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contains:
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const: snps,dwc3
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interrupts:
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minItems: 1
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maxItems: 3
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clocks:
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description:
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In general the core supports three types of clocks. bus_early is a
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SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
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PHY is suspended. suspend clocks a small part of the USB3 core when
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SS PHY in P3. But particular cases may differ from that having less
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or more clock sources with another names.
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clock-names:
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contains:
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anyOf:
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- enum: [bus_early, ref, suspend]
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- true
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usb-phy:
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minItems: 1
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items:
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- description: USB2/HS PHY
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- description: USB3/SS PHY
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phys:
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minItems: 1
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items:
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- description: USB2/HS PHY
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- description: USB3/SS PHY
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phy-names:
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minItems: 1
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items:
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- const: usb2-phy
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- const: usb3-phy
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resets:
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minItems: 1
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snps,usb2-lpm-disable:
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description: Indicate if we don't want to enable USB2 HW LPM
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type: boolean
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snps,usb3_lpm_capable:
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description: Determines if platform is USB3 LPM capable
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type: boolean
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snps,dis-start-transfer-quirk:
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description:
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When set, disable isoc START TRANSFER command failure SW work-around
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for DWC_usb31 version 1.70a-ea06 and prior.
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type: boolean
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snps,disable_scramble_quirk:
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description:
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True when SW should disable data scrambling. Only really useful for FPGA
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builds.
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type: boolean
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snps,has-lpm-erratum:
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description: True when DWC3 was configured with LPM Erratum enabled
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type: boolean
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snps,lpm-nyet-threshold:
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description: LPM NYET threshold
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$ref: /schemas/types.yaml#/definitions/uint8
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snps,u2exit_lfps_quirk:
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description: Set if we want to enable u2exit lfps quirk
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type: boolean
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snps,u2ss_inp3_quirk:
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description: Set if we enable P3 OK for U2/SS Inactive quirk
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type: boolean
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snps,req_p1p2p3_quirk:
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description:
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When set, the core will always request for P1/P2/P3 transition sequence.
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type: boolean
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snps,del_p1p2p3_quirk:
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description:
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When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
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occur.
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type: boolean
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snps,del_phy_power_chg_quirk:
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description: When set core will delay PHY power change from P0 to P1/P2/P3.
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type: boolean
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snps,lfps_filter_quirk:
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description: When set core will filter LFPS reception.
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type: boolean
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snps,rx_detect_poll_quirk:
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description:
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when set core will disable a 400us delay to start Polling LFPS after
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RX.Detect.
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type: boolean
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snps,tx_de_emphasis_quirk:
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description: When set core will set Tx de-emphasis value
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type: boolean
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snps,tx_de_emphasis:
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description:
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The value driven to the PHY is controlled by the LTSSM during USB3
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Compliance mode.
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$ref: /schemas/types.yaml#/definitions/uint8
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snps,dis_u3_susphy_quirk:
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description: When set core will disable USB3 suspend phy
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type: boolean
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snps,dis_u2_susphy_quirk:
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description: When set core will disable USB2 suspend phy
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type: boolean
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snps,dis_enblslpm_quirk:
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description:
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When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
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to the PHY.
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type: boolean
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snps,dis-u1-entry-quirk:
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description: Set if link entering into U1 needs to be disabled
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type: boolean
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snps,dis-u2-entry-quirk:
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description: Set if link entering into U2 needs to be disabled
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type: boolean
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snps,dis_rxdet_inp3_quirk:
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description:
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When set core will disable receiver detection in PHY P3 power state.
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type: boolean
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snps,dis-u2-freeclk-exists-quirk:
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description:
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When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
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PHY doesn't provide a free-running PHY clock.
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type: boolean
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snps,dis-del-phy-power-chg-quirk:
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description:
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When set core will change PHY power from P0 to P1/P2/P3 without delay.
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type: boolean
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snps,dis-tx-ipgap-linecheck-quirk:
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description: When set, disable u2mac linestate check during HS transmit
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type: boolean
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snps,parkmode-disable-ss-quirk:
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description:
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When set, all SuperSpeed bus instances in park mode are disabled.
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type: boolean
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snps,dis_metastability_quirk:
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description:
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When set, disable metastability workaround. CAUTION! Use only if you are
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absolutely sure of it.
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type: boolean
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snps,dis-split-quirk:
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description:
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When set, change the way URBs are handled by the driver. Needed to
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avoid -EPROTO errors with usbhid on some devices (Hikey 970).
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type: boolean
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snps,is-utmi-l1-suspend:
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description:
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True when DWC3 asserts output signal utmi_l1_suspend_n, false when
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asserts utmi_sleep_n.
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type: boolean
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snps,hird-threshold:
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description: HIRD threshold
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$ref: /schemas/types.yaml#/definitions/uint8
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snps,hsphy_interface:
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description:
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High-Speed PHY interface selection between UTMI+ and ULPI when the
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DWC_USB3_HSPHY_INTERFACE has value 3.
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$ref: /schemas/types.yaml#/definitions/uint8
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enum: [utmi, ulpi]
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snps,quirk-frame-length-adjustment:
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description:
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Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
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length adjustment when the fladj_30mhz_sdbnd signal is invalid or
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incorrect.
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$ref: /schemas/types.yaml#/definitions/uint32
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snps,rx-thr-num-pkt-prd:
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description:
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Periodic ESS RX packet threshold count (host mode only). Set this and
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snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.4) to enable periodic ESS RX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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snps,rx-max-burst-prd:
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description:
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Max periodic ESS RX burst size (host mode only). Set this and
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snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.4) to enable periodic ESS RX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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snps,tx-thr-num-pkt-prd:
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description:
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Periodic ESS TX packet threshold count (host mode only). Set this and
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snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.3) to enable periodic ESS TX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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snps,tx-max-burst-prd:
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description:
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Max periodic ESS TX burst size (host mode only). Set this and
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snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.3) to enable periodic ESS TX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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tx-fifo-resize:
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description: Determines if the FIFO *has* to be reallocated
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deprecated: true
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type: boolean
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snps,incr-burst-type-adjustment:
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description:
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Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
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burst type enable and INCRx type. A single value means INCRX burst mode
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enabled. If more than one value specified, undefined length INCR burst
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type will be enabled with burst lengths utilized up to the maximum
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of the values passed in this property.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 8
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uniqueItems: true
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items:
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enum: [1, 4, 8, 16, 32, 64, 128, 256]
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
|
||||
|
||||
examples:
|
||||
- |
|
||||
usb@4a030000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x4a030000 0xcfff>;
|
||||
interrupts = <0 92 4>;
|
||||
usb-phy = <&usb2_phy>, <&usb3_phy>;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
- |
|
||||
usb@4a000000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x4a000000 0xcfff>;
|
||||
interrupts = <0 92 4>;
|
||||
clocks = <&clk 1>, <&clk 2>, <&clk 3>;
|
||||
clock-names = "bus_early", "ref", "suspend";
|
||||
phys = <&usb2_phy>, <&usb3_phy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
};
|
||||
...
|
||||
Loading…
Reference in New Issue