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drm/i915: rename 'ring' where it refers to an engine or engine_id

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'ring' is an old deprecated term for a GPU engine. Chris Wilson wants to
use the name for what is currently known as an intel_ringbuffer, but it
will be dreadfully confusing if some rings are ringbuffers but other
rings are still engines. So this patch changes the names of a bunch of
parameters called 'ring' to either 'engine' or 'engine_id' according to
what they actually are.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469034967-15840-3-git-send-email-david.s.gordon@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Dave Gordon 2016-07-20 18:16:06 +01:00 committed by Chris Wilson
parent bbdc070a79
commit 38a0f2db5b
4 changed files with 11 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
drivers/gpu/drm/i915/intel_mocs.c
View file

@ -204,9 +204,9 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
return result;
}
static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
{
switch (ring) {
switch (engine_id) {
case RCS:
return GEN9_GFX_MOCS(index);
case VCS:
@ -218,7 +218,7 @@ static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
case VCS2:
return GEN9_MFX1_MOCS(index);
default:
MISSING_CASE(ring);
MISSING_CASE(engine_id);
return INVALID_MMIO_REG;
}
}

2
drivers/gpu/drm/i915/intel_mocs.h
View file

@ -54,6 +54,6 @@
int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req);
void intel_mocs_init_l3cc_table(struct drm_device *dev);
int intel_mocs_init_engine(struct intel_engine_cs *ring);
int intel_mocs_init_engine(struct intel_engine_cs *engine);
#endif

2
drivers/gpu/drm/i915/intel_ringbuffer.c
View file

@ -1595,7 +1595,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
}
static void
gen5_seqno_barrier(struct intel_engine_cs *ring)
gen5_seqno_barrier(struct intel_engine_cs *engine)
{
/* MI_STORE are internally buffered by the GPU and not flushed
* either by MI_FLUSH or SyncFlush or any other combination of

12
drivers/gpu/drm/i915/intel_ringbuffer.h
View file

@ -197,14 +197,14 @@ struct intel_engine_cs {
u32 irq_keep_mask; /* always keep these interrupts */
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
void (*irq_enable)(struct intel_engine_cs *ring);
void (*irq_disable)(struct intel_engine_cs *ring);
void (*irq_enable)(struct intel_engine_cs *engine);
void (*irq_disable)(struct intel_engine_cs *engine);
int (*init_hw)(struct intel_engine_cs *ring);
int (*init_hw)(struct intel_engine_cs *engine);
int (*init_context)(struct drm_i915_gem_request *req);
void (*write_tail)(struct intel_engine_cs *ring,
void (*write_tail)(struct intel_engine_cs *engine,
u32 value);
int __must_check (*flush)(struct drm_i915_gem_request *req,
u32 invalidate_domains,
@ -216,14 +216,14 @@ struct intel_engine_cs {
* seen value is good enough. Note that the seqno will always be
* monotonic, even if not coherent.
*/
void (*irq_seqno_barrier)(struct intel_engine_cs *ring);
void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
int (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
u64 offset, u32 length,
unsigned dispatch_flags);
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
#define I915_DISPATCH_RS 0x4
void (*cleanup)(struct intel_engine_cs *ring);
void (*cleanup)(struct intel_engine_cs *engine);
/* GEN8 signal/wait table - never trust comments!
* signal to signal to signal to signal to signal to